Taiwan Semiconductor Manufacturing Comp. Ltd.

Worldwide Semiconductor Manufacturing Corporation

Pao-Kang Niu

Pei-Haw Tsao

Liang-Chen Lin

Bill Kiang

I-Tai Liu

Shang-Yun Hou

Shin-Puu Jeng

Hao-Yi Tsai

Jian-Hsing Lee

Chun-Hung Chen

Chia-Lun Tsai

Chung Yu Wang

Yung-Kuan Hsiao

Bih-Tiao Lin

Ko-Yi Lee

Chang-Sheng Lee

Sen-Nan Lee

Lin Yu-Ting

A system-in-package (SiP) package is provided. In one embodiment, the SiP package comprises a substrate having a first surface and a second surface opposite the first surface, the substrate having a set of bond wire studs on bond pads formed on the second surface thereof; a first semiconductor chip having a first surface and a second surface opposite the first surface, wherein the first surface of the first semiconductor chip is mounted to the second surface of the substrate by means of solder bumps; an underfill material disposed between the first semiconductor chip and the substrate, encapsulating the solder bumps; a second semiconductor chip having a first surface and a second surface opposite the first surface, wherein the first surface of the second semiconductor chip is mounted to the second surface of the first semiconductor chip; and a set of bond wires electrically coupled from the second semiconductor chip to the set of bond wire studs on the substrate.

System-in-package packaging for minimizing bond wire contamination and yield loss

A package structure includes a substrate; a die over and flip bonded on the substrate; a heat sink over the die; and one or more spacer separating the heat sink from the substrate.

Flip chip packages with spacers separating heat sinks and substrates

An improved via arrangement for a bonding pad structure is disclosed comprising an array of vias surrounded by a line via. The line via provides a barrier to cracks in the dielectric layer encompassing the via array. Although cracks are able to spread relatively unhindered between the vias of the via array, they are blocked by the line via and thus can not spread to neighboring regions of the chip or wafer. The line via can be provided in a variety of shapes and dimensions, to suit a desired application. Additionally, due to its substantially uninterrupted length, the line via provides added strength to the bond pad.

Bond pad design to minimize dielectric cracking

Solder bump structures for semiconductor device packaging is provided. In one embodiment, a semiconductor device comprises a substrate having a bond pad and a first passivation layer formed thereabove, the first passivation layer having an opening therein exposing a portion of the bond pad. A metal pad layer is formed on a portion of the bond pad, wherein the metal pad layer contacts the bond pad. A second passivation layer is formed above the metal pad layer, the second passivation layer having an opening therein exposing a portion of the metal pad layer. A patterned and etched polyimide layer is formed on a portion of the metal pad layer and a portion of the second passivation layer. A conductive layer is formed above a portion of the etched polyimide layer and a portion of the metal pad layer, wherein the conductive layer contacts the metal pad layer. A conductive bump structure is connected to the conductive layer.

Solder bump structure and method of manufacturing same

A semiconductor device includes a first circuit, a first seal ring and at least one first notch. The first seal ring surrounds the first circuit. The first notch cuts the first seal ring. Specifically, the first notch includes an inner opening, an outer opening and a connecting groove. The inner opening is located on the inner side of the first seal ring. The outer opening is located on the outer side of the first seal ring. The outer opening and the inner opening are not aligned. The connecting groove connects the inner opening and the outer opening.

Seal ring in semiconductor device

A bump pattern design for flip chip semiconductor packages includes a pattern of contact pads formed on a package substrate. Each contact pad is adapted to receive a corresponding solder bump from a semiconductor chip attached thereto. The pattern includes a central portion and a peripheral portion with a transition portion therebetween. The transition portion has a lower pattern density than the central portion and peripheral portions. In the peripheral portion is at least one outer portion having a pattern density less than the average pattern density of the central portion. The outer portions of reduced pattern density may be the corner sections in a rectangular bump pattern and may further include channels that are void of contact pads. The peripheral portion may include an average pitch between most of the rows and columns, but also an increased pitch between some adjacent rows and columns.

Bump pattern design for flip chip semiconductor package

A bonding pad structure and fabrication method thereof. A bonding pad is substantially surrounded and insulated by a dielectric layer, wherein the bonding pad is formed of at least one first conductive layer having a wiring layer with a stripe layout and a first edge portion, a second conductive layer having a wire bonding portion and a second edge portion and a plurality of plugs electrically connecting the wiring layer and the wire bonding portion. A conductive structure of an array of metal plugs or a metal damascene structure is formed to connect the first edge portion and the second edge portion, thereby preventing burn out of the first edge portion during an ESD event.

Bonding pad structure and method of forming the same

An auto slurry deliver fine-tune system and a method using the system is discloses. A slurry flow system varies the flow rate of the slurry in a CMP system and the distance between the slurry injector and the polish head of the CMP system. A current detect system detects the current driving the turn-table of the CMP system. Moreover, a judgement system determines whether the current is minimum in order to determine that the flow rate and the distance are optima.

Auto slurry deliver fine-tune systems for chemical-mechanical-polishing process and method of using the system

Auto slurry deliver fine-tune system for chemical-mechanical-polishing process and method of using the system

A method for planarizing a semiconductor wafer. An insulation layer is formed over the wafer. A spin-on-glass layer is coated over the insulation layer. Subsequently, the spin-on-glass layer is baked to smooth out its upper surface. A chemical-mechanical polishing process is carried out to planarize the insulation layer. The method eliminates recess cavities in the more loosely packed device region of the insulation layer after a planarization process.

Growing community of inventors

Hsinchu, Taiwan

Pao-Kang Niu