Taiwan Semiconductor Manufacturing Comp. Ltd.

Pai-Wei Wan

Ru-Gun Liu

Chih-Ming Lai

Ken-Hsien Hsieh

Wen-Chun Huang

Wen-Li Cheng

Disclosed is a method of fabricating an integrated circuit (IC) using a multiple (N&#x3e;2) patterning technique. The method provides a layout of the IC having a set of IC features. The method further includes deriving a graph from the layout, the graph having vertices connected by edges, the vertices representing the IC features, and the edges representing spacing between the IC features. The method further includes selecting vertices, wherein the selected vertices are not directly connected by an edge, and share at least one neighboring vertex that is connected by N edges. The method further includes using a computerized IC tool to merge the selected vertices, thereby reducing a number of edges connecting the neighboring vertex to be below N. The method further includes removing a portion of the vertices that are connected by less than N edges.

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Hsin-Chu, Taiwan

Pai-Wei Wan