Micron Technology Incorporated

International Business Machines Corporation

Pai-Hung Pan

Kirk D Prall

Tyler A Lowrey

Li Li

Zhiqiang (Jeff) Wu

Luan C Tran

Sujit Sharan

Thomas Arthur Figura

Howard E Rhodes

Kunal R Parekh

Werner Juengling

Pierre C Fazan

Alan R Reinberg

Aftab A Ahmad

Kin F Ma

Yongjun Jeff Hu

Ravi T Iyer

Karl M Robinson

Scott Jeffrey DeBoer

Yong-Jun Hu

Louie Liu

Randhir P Thakur

Michael L Nuttall

David L Harmon

Mark Klare

Jack Allan Mandelman

Son Van Nguyen

Er-Xuan Ping

Randhir P S Thakur

Tue H Nguyen

Whonchee Lee

David M Dobuzinsky

Donald M Kenney

Nanseng Jeng

Hing Wong

Brian J Machesney

Srinandan R Kasi

Vishnu Kumar Agarwal

Scott G Meikle

Martin Ceredig Roberts

Weimin Li

Jerome Brett Lasky

Michael D Armacost

Kevin J Stewart

Christopher W Hill

David L Johnson

Alan C Thomas

Stephen Frank Geissler

Henry J Geipel, Jr

Nancy T Pascoe

John R Abernathey

John F Rembetski

Josef W Korejwa

Gurtei Singh Sandhu

Thomas A Figura

Louie Liù

Kevin M Golden

Michael M Armacost

Charles A Paquette

Oxidation methods and resulting structures including providing an oxide layer on a substrate and then reoxidizing the oxide layer by vertical ion bombardment of the oxide layer in an atmosphere containing at least one oxidant. The oxide layer may be provided over diffusion regions, such as source and drain regions, in a substrate. The oxide layer may overlie the substrate and is proximate a gate structure on the substrate. The at least one oxidant may be oxygen, water, ozone, or hydrogen peroxide, or a mixture thereof. These oxidation methods provide a low-temperature oxidation process, less oxidation of the sidewalls of conductive layers in the gate structure, and less current leakage to the substrate from the gate structure.

Methods for reoxidizing an oxide and for fabricating semiconductor devices

A shallow isolation trench structure and methods of forming the same wherein the method of formation comprises a layered structure of a buffer film layer over a dielectric layer that is atop a semiconductor substrate. The buffer film layer comprises a material that is oxidation resistant and can be etched selectively to oxide films. The layered structure is patterned with a resist material and etched to form a shallow trench. A thin oxide layer is formed in the trench and the buffer film layer is selectively etched to move the buffer film layer back from the corners of the trench. An isolation material is then used to fill the shallow trench and the buffer film layer is stripped to form an isolation structure. When the structure is etched by subsequent processing step(s), a capped shallow trench isolation structure that covers the shallow trench corners is created.

Semiconductor devices structures including an isolation structure

Structures including an at least partially reoxidized oxide material

Methods for forming isolation structures for semiconductor devices

Oxidation methods and resulting structures including providing an oxide layer on a substrate and then re-oxidizing the oxide layer by vertical ion bombardment of the oxide layer in an atmosphere containing at least one oxidant. The oxide layer may be provided over diffusion regions, such as source and drain regions, in a substrate. The oxide layer may overlie the substrate and is proximate a gate structure on the substrate. The at least one oxidant may be oxygen, water, ozone, or hydrogen peroxide, or a mixture thereof. These oxidation methods provide a low-temperature oxidation process, less oxidation of the sidewalls of conductive layers in the gate structure, and less current leakage to the substrate from the gate structure.

Ion-assisted oxidation methods and the resulting structures

A semiconductor processing method of forming a conductive gate or gate line over a substrate includes, a) forming a conductive gate over a gate dielectric layer on a substrate, the gate having sidewalls and an interface with the gate dielectric layer; b) electrically insulating the gate sidewalls; and c) after electrically insulating the gate sidewalls, exposing the substrate to oxidizing conditions effective to oxidize at least a portion of the gate interface with the gate dielectric layer. According to one aspect of the invention, the step of exposing the substrate to oxidizing conditions is conducted after provision of a first insulating material and subsequent anisotropic etch thereof to insulate the gate sidewalls. According to another aspect of the invention, the step of exposing the substrate to oxidizing conditions is conducted after provision of first and second insulating materials and subsequent anisotropic etch thereof to insulate the gate sidewalls. According to another aspect of the invention, the step of exposing the substrate to oxidizing conditions is conducted after provision and subsequent anisotropic etch of a first insulating material, followed by provision and subsequent anisotropic etch of a second insulating material.

Semiconductor constructions

Methods, apparatuses and substrate assembly structures for mechanical and chemical-mechanical planarizing processes used in the manufacturing microelectronic-device substrate assemblies. One aspect of the invention is directed toward a method for planarizing a microelectronic-device substrate assembly by removing material from a surface of the substrate assembly, detecting a first change in drag force between the substrate assembly and a polishing pad indicating that the substrate surface is planar, and identifying a second change in drag force between the substrate assembly and the polishing pad indicating that the planar substrate surface is at the endpoint elevation. After the second change in drag force is identified, the planarization process is stopped. The first change in drag force between the substrate assembly and the planarizing medium is preferably detected by measuring a first change in the electrical current through a drive motor driving a substrate holder carrying the substrate assembly and/or a table carrying the polishing pad. The second change in drag force between the substrate assembly and the polishing pad may be identified by detecting a second change in the drive motor current or measuring a second change in the temperature of the planarizing solution or the polishing pad.

Methods, apparatuses, and substrate assembly structures for fabricating microelectronic components using mechanical and chemical-mechanical planarization processes

A method for forming a gate stack which minimizes or eliminates damage to the gate dielectric layer and/or silicon substrate during the gate stack formation by the reduction of the temperature during formation. The temperature reduction prevents the formation of silicon clusters within the metallic silicide film in the gate stack which has been found to cause damage during the gate etch step. The present invention also includes methods for dispersing silicon clusters prior to the gate etch step.

Technique for elimination of pitting on silicon substrate during gate stack etch using material in a non-annealed state

Method of forming a gate stack

Oxidation methods, and resulting structures, comprising providing an oxide layer on a substrate and then re-oxidizing the oxide layer by vertical ion bombardment of the oxide layer in an atmosphere containing at least one oxidant. The oxide layer may be provided over diffusion regions, such as source and drain regions, in a substrate. The oxide layer may overlie the substrate and is proximate a gate structure on the substrate. The at least one oxidant may be oxygen, water, ozone, or hydrogen peroxide, or a mixture thereof. These oxidation methods provide a low-temperature oxidation process, less oxidation of the sidewalls of conductive layers in the gate structure, and less current leakage to the substrate from the gate structure.

Semiconductor device structures formed by ion-assisted oxidation

Methods of forming a gate stack that is void of silicon clusters within a metallic silicide film thereof

A method of forming an isolation structure comprising forming n-type areas and/or p-type areas implanted respectively therein on a first surface of a substrate. A pad oxide film is grown on the first surface of the substrate covering the p-wells and/or n-wells. A diffusion barrier(s) is deposited on the first surface of the substrate and a second surface of the substrate to form an encapsulated structure. The encapsulated structure is annealed to activate the n-type and/or p-type areas. A mask material is applied over the diffusion barrier on the first surface of the substrate to define active device areas and a dry etch process is used to etch away the unmasked potions of the diffusion barrier. The mask material is stripped and a field oxide is grown on the first surface of the substrate. A portion of the field oxide and all of the diffusion barrier is removed, resulting in active areas surrounded by a field isolation structure.

Intermediate structure having a silicon barrier layer encapsulating a semiconductor substrate

A semiconductor processing method of forming a conductive gate or gate line over a substrate includes, a) forming a conductive gate over a gate dielectric layer on a substrate, the gate having sidewalls and an interface with the gate dielectric layer; b) electrically insulating the gate sidewalls; and c) after electrically insulating the gate sidewalls, exposing the substrate to oxidizing conditions effective to oxidize at least a portion of the gate interface with the gate dielectric layer. According to one aspect of the invention, the step of exposing the substrate to oxidizing conditions is conducted after provision of a first insulating material and subsequent anisotropic etch thereof to insulate the gate sidewalls.

Semiconductor processing methods of forming a conductive gate and line

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