International Business Machines Corporation

Other

Infineon Technologies Ag

Padraic C Shafer

Rajarao Jammy

Carl John Radens

Daniel C Edelstein

Michael Patrick Chudzik

Richard Anthony Conti

David M Dobuzinsky

Joseph Francis Shepard, Jr

Alexander William Simpson

Kenneth T Settlemyer, Jr

Werner Robl

Roy Charles Iggulden

Gill Yong Lee

Kia-Seng Low

Peter Wrschka

Prakash Chimanlal Dev

Jack Allan Mandelman

Laertis Economikos

Kwong Hon Wong

Michael P Belyansky

Rama Divakaruni

Jay William Strane

Thomas Goebel

Michael M Iwatake

Donna Diane Miura

Kenneth T Settlemeyer, Jr

Chet Dziobkowski

Kwong Hon (Keith) Wong

In a method of fabricating a metallization structure during formation of a microelectronic device, the improvement of reducing metal shorts in blanket metal deposition layers later subjected to reactive ion etching, comprising:

Low Cu percentages for reducing shorts in AlCu lines

Disclosed herein is a method, in an integrated, of forming a high-K node dielectric of a trench capacitor and a trench sidewall device dielectric at the same time. The method includes forming a trench in a single crystal layer of a semiconductor substrate, and forming an isolation collar along a portion of the trench sidewall, wherein the collar has a top below the top of the trench in the single crystal layer. Then, at the same time, a high-K dielectric is formed along the trench sidewall, the high-K dielectric extending in both an upper portion of the trench including above the isolation collar and in a lower portion of the trench below the isolation collar. The top of the isolation collar is then etched back to expose a portion of the single crystal substrate along the sidewall, and then, a node electrode is formed in conductive contact with the exposed sidewall and also in contact with the high-K dielectric in the lower portion, such that the high-K dielectric remains as a trench sidewall dielectric in the upper portion of the sidewall. In a DRAM memory cell structure, the trench sidewall dielectric may then be used as a gate dielectric of a vertical transistor which accesses the trench storage capacitor in the trench.

Semiconductor method and structure for simultaneously forming a trench capacitor dielectric and trench sidewall device dielectric

Isolation trenches and capacitor trenches containing vertical FETs (or any prior levels p-n junctions or dissimilar material interfaces) having an aspect ratio up to 60 are filled with a process comprising: applying a spin-on material based on silazane and having a low molecular weight; pre-baking the applied material in an oxygen ambient at a temperature below about 450 deg C.; converting the stress in the material by heating at an intermediate temperature between 450 deg C. and 800 deg C. in an H2O ambient; and heating again at an elevated temperature in an O2 ambient, resulting in a material that is stable up to 1000 deg C., has a compressive stress that may be tuned by variation of the process parameters, has an etch rate comparable to oxide dielectric formed by HDP techniques, and is durable enough to withstand CMP polishing.

Filling high aspect ratio isolation structures with polysilazane based material

A structure and method for an insulator layer having carbon-graded layers above a substrate is disclosed, wherein the concentration of carbon increases in each successive carbon-graded layer above the substrate. The insulator comprises a low-k dielectric having a dielectric constant less than 3.3. The carbon-graded layer increases adhesion between the substrate and the insulator and between the insulator and the conductor layer. The structure may also include stabilization interfaces between the carbon-graded layers. More specifically, the carbon-graded layers include a first layer adjacent the substrate having a carbon content between about 5% and 20%, a second layer above the first layer having a carbon content between about 10% and 30%, and a third layer above the second layer having a carbon content between about 20% and 40%.

Carbon-graded layer for improved adhesion of low-k dielectrics to silicon substrates

A method of filling a damascene structure with liner and W characterized by improved resistance and resistance spread and adequate adhesion comprising: a given damascene structure coated by a liner which purposely provides poor step coverage into the afore mentioned structure, followed by a CVD W deposition, and followed by a metal isolation technique.

Liner with poor step coverage to improve contact resistance in W contacts

The present invention is a method and structure for fabricating a trench capacitor within a semiconductor substrate having a buried plate electrode formed of metal silicide. A collar is formed in a trench etched into a substrate; a conformal metal film is deposited thereover, and is annealed to form a silicide that is self-aligned to the collar. Silicide will not be formed on the collar, pads and other areas where the silicon is not directly exposed and hence the metal layer can be removed from these areas by selective etching.

Method and structure for salicide trench capacitor plate electrode

Growing community of inventors

Beacon, NY, United States of America

Padraic C Shafer