Cypress Semiconductor Corporation

Padma Nagaraja

Shiva P Gowni

Purushothaman Ramakrishnan

The output (3) of a level shifter (1) is split into two paths (4,5) with a delay (.tau..sub.1, .tau..sub.2) being introduced into at least one path to enable rise delay and fall delay to be controlled independently of one another. In the context of an integrated circuit which includes a memory device, the use of an additional path allows control of the set-up and hold times in that one transition can be speeded up or slowed down independently of the other transition to achieve the best possible set-up and hold times.

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Bengaluru, India

Padma Nagaraja