Apple Inc.

D2s, Inc.

Gauda, Inc.

Guada, Inc.

P Jeffrey Ungar

Thomas Charles Greening

William C Athas

Jeffrey G Koller

Akira Fujimura

Ilhami H Torunoglu

Nagesh Shirali

Nils E Mattisson

Steven Charles Michalske

Eric G Smith

Hironobu Matsumoto

J Douglas Field

Richard M Mank

Louis Luh

Heather R Sullens

Derek G Pyne

Methods for reticle enhancement technology include inputting a target wafer pattern, the target wafer pattern spanning an entire design area, and iterating a proposed mask for the entire design area until the proposed mask meets criteria towards producing the target wafer pattern. Each iteration includes calculating a predicted wafer pattern from the proposed mask. The calculating comprises calculating a cost and derivative data, the cost and the derivative data being based on comparing the predicted wafer pattern to the target wafer pattern. The cost further comprises specifications for mask manufacturability.

Methods for modeling of a design in reticle enhancement technology

Systems for reticle enhancement technology (RET) for use with variable shaped beam (VSB) lithography include a device configured to determine an initial mask pattern from a desired pattern for a substrate; a device configured to calculate a first substrate pattern from the initial mask pattern; a device configured to determine an initial set of VSB shots based on the initial mask pattern; a device configured to calculate a second substrate pattern from a simulated mask pattern calculated with the initial set of VSB shots; a device configured to compare the first substrate pattern with the second substrate pattern; and a device configured to adjust the initial set of VSB shots until the second substrate pattern and the first substrate pattern are within a predetermined tolerance, creating an adjusted set of VSB shots.

Methods and systems for reticle enhancement technology of a design pattern to be manufactured on a substrate

Methods and systems for fracturing a pattern to be exposed on a surface using variable shaped beam (VSB) lithography include inputting an initial pattern; calculating a first substrate pattern from the initial pattern; overlaying the initial pattern with a two-dimensional grid, wherein an initial set of VSB shots are formed by a union of the initial pattern with locations on the grid; and merging two or more adjacent shots in the initial set of VSB shots to create a larger shot in a modified set of VSB shots; and outputting the modified set of VSB shots. The methods and systems also include calculating a calculated pattern to be exposed on the surface with the modified set of VSB shots; and calculating a second substrate pattern from the calculated pattern to be exposed on the surface.

Methods for reticle enhancement technology (RET) for use with variable shaped beam (VSB) lithography include determining an initial mask pattern from a desired pattern for a substrate; calculating a first substrate pattern from the initial mask pattern; determining an initial set of VSB shots that will form the initial mask pattern; calculating a simulated mask pattern from the initial set of VSB shots; calculating a second substrate pattern from the simulated mask pattern; and adjusting the initial set of VSB shots, wherein the adjusting of the initial set of VSB shots creates an adjusted set of VSB shots.

Method for reticle enhancement technology of a design pattern to be manufactured on a substrate

Methods for reticle enhancement technology include representing a target wafer pattern or a predicted wafer pattern as a smooth function captured as a function sample array (FSA). The FSA is an array of sampled values of the smooth function, which is a continuous differentiable function. Methods also include providing a continuous tone mask (CTM), wherein the CTM is used to produce the predicted wafer pattern, the predicted wafer pattern spanning an entire design area.

Methods for fracturing a pattern to be exposed on a surface using variable shaped beam (VSB) lithography include inputting an initial pattern; calculating a first substrate pattern from the initial pattern; overlaying the initial pattern with a two-dimensional grid, wherein an initial set of VSB shots are formed by a union of the initial pattern with locations on the grid; and merging two or more adjacent shots in the initial set of VSB shots to create a larger shot in a modified set of VSB shots; and outputting the modified set of VSB shots. The method also includes calculating a calculated pattern to be exposed on the surface with the modified set of VSB shots; and calculating a second substrate pattern from the calculated pattern to be exposed on the surface.

Methods for reticle enhancement technology (RET) for use with variable shaped beam (VSB) lithography include inputting a desired pattern to be formed on a substrate; determining an initial mask pattern from the desired pattern for the substrate; optimizing the initial mask pattern for wafer quality using a VSB exposure system; and outputting the optimized mask pattern. Methods for fracturing a pattern to be exposed on a surface using VSB lithography include inputting an initial pattern; overlaying the initial pattern with a two-dimensional grid, wherein an initial set of VSB shots are formed by the union of the initial pattern with locations on the grid; merging two or more adjacent shots in the initial set of VSB shots to create a larger shot in a modified set of VSB shots; and outputting the modified set of VSB shots.

Methods for iteratively optimizing a two-dimensioned tiled area such as a lithographic mask include determining a halo area around each tile in the tiled area. An extended tile is made of a tile and a halo area. Each extended tile in the tiled area is iterated until a criterion is satisfied or a maximum number of iterations is met. Optimizing the extended tile produces a pattern for the tile such that at a perimeter of the tile, the pattern matches adjacent patterns that are calculated at perimeters of adjacent tiles.

Methods for reticle enhancement technology (RET) include inputting a target wafer pattern, where the target wafer pattern spans an entire design area. The entire design area is divided into a plurality of tiles, each tile having a halo region surrounding the tile. A proposed mask for the entire design area is iterated until the proposed mask meets criteria towards producing the target wafer pattern. Each iteration includes calculating a predicted wafer pattern for a subset of the plurality of tiles; and updating the proposed mask for that tile; where all tiles in the subset are calculated before the next iteration.

Modeling of a design in reticle enhancement technology

Methods for reticle enhancement technology (RET) include representing a target wafer pattern or a predicted wafer pattern as a smooth function captured as a function sample array, which is an array of function values. A continuous tone mask (CTM) is provided, where the CTM is used to produce the predicted wafer pattern. Methods for RET also include inputting a target wafer pattern, where the target wafer pattern spans an entire design area. The entire design area is divided into a plurality of tiles, each tile having a halo region surrounding the tile. A proposed mask for the entire design area is iterated until the proposed mask meets criteria towards producing the target wafer pattern. Each iteration includes calculating a predicted wafer pattern for a subset of the plurality of tiles; and updating the proposed mask for that tile; where all tiles in the subset are calculated before the next iteration.

A system for tracking the capacity of a battery in a portable electronic device is described. While the portable electronic device remains plugged in to a power adapter, the system estimates the capacity of the battery by performing the following operations. The system measures a first open-circuit voltage for the battery while the battery rests at a first state of charge. Next, the system causes the battery to transition to a second state of charge. While the battery transitions to the second state of charge, the system integrates a current through the battery to determine a net change in charge for the battery. Next, the system measures a second open-circuit voltage for the battery while the battery rests at the second state of charge. Finally, the system estimates a capacity for the battery based on the first open-circuit voltage, the second open-circuit voltage and the net change in charge. This capacity measurement is repeated and the multiple results are fit to a line. The slope of fitted line is then used to estimate how the true battery capacity has faded since last measured using traditional methods that require the battery to be rested at a low state of charge.

Tracking fading battery capacity in a plugged-in portable electronic device

Some embodiments of the present invention provide a system that adaptively charges a battery, wherein the battery is a lithium-ion battery which includes a transport-limiting electrode governed by diffusion, an electrolyte separator and a non-transport-limiting electrode. During operation, the system determines a lithium surface concentration at an interface between the transport-limiting electrode and the electrolyte separator based on a diffusion time for lithium in the transport-limiting electrode. Next, the system calculates a charging current or a charging voltage for the battery based on the determined lithium surface concentration. Finally, the system applies the charging current or the charging voltage to the battery.

Diffusion-limited adaptive battery charging

The disclosed embodiments provide a system that manages use of a battery in a portable electronic device. During operation, the system obtains a voltage of the battery and a state-of-charge of the battery and calculates an effective C-rate of the battery using the voltage and the state-of-charge. Next, the system uses the effective C-rate to estimate an inaccessible capacity of the battery. Finally, the system manages use of the battery with the portable electronic device based on the inaccessible capacity.

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Sunnyvale, CA, United States of America

P Jeffrey Ungar