International Business Machines Corporation

Otto M Wagner

Helmut Schettler

Juergen Pille

Thomas Ludwig

Sebastian Ehrenreich

Rolf Sautter

Yuen H Chan

Anthony Gus Aipperspach

Derick Gardner Behrends

Erich Klink

Werner O Haug

Guenter Mayer

Jatinder K Wadhwa

Rainer Zuhlke

Rainer Stahl

Karl E Kroll

Torsten Mahnke

Chad Allen Adams

Antonio R Pelella

Wolfgang Penth

Arthur D Tuminaro

Stefan Buettner

John R Rawlins

Gerhard Hellner

Timothy J Charest

Rainer Zuehlke

Kurt Pollmann

Heinrich K Lindner

Thomas Froehnel

Wolf-Dieter Lohlein

Peter Knott

Klaus Klein

Uwe Schulz

A method to read and write at least one static memory cell is provided, said cell comprising a cross-coupled inverter pair and two pass-devices wherein said method is characterized in that during read only one of the two pass-devices is selected, while for write both pass-devices are selected. Furthermore, a circuit to read and write at least one static memory cell is described, said cell comprising a cross-coupled inverter pair and two pass-devices. Said circuit is characterized in that for each pass-device of the cell an individual wordline is connected with a gate of the particular pass-device, wherein both wordlines are selected for write and a single wordline is selected for read.

Single-ended read and differential write scheme

A circuit () combining level shift function with gated reset is described, performing a simple logic function with inputs supplied from a lower voltage (VD) and a drive out at its output () with a higher voltage (VC). Said circuit () comprises a gated reset scheme plus devices () for logic function.

Circuit combining level shift function with gated reset

A design structure embodied in a machine readable medium to improve performance of an SRAM cell or an SRAM array comprising a plurality of SRAM cells is described. The design structure includes a write circuit for an SRAM cell or an SRAM array. The write circuit includes a gate to switch the write circuit on and off. The cell is supplied by a first, higher voltage. The cell is accessible for read and write operations via at least one bit line connected to a write circuit. The cell is further addressable by at least one word line in order to access it by the bit line. To access the cell for read or write operations, the word line is supplied by the first, higher voltage and the bit line is supplied by a second, lower voltage. During write operations, the write circuit is driven by the first, higher voltage while the bit lines are still at the lower voltage.

Design structure for improving performance of SRAM cells, SRAM cell, SRAM array, and write circuit

A method to improve performance of an SRAM cell or an SRAM array comprising a plurality of SRAM cells is described. The cell is supplied by a first, higher voltage. The cell is accessible for read and write operations via at least one bit line connected to a write circuit. The cell is further addressable by at least one word line in order to access it by the bit line. To access the cell for read or write operations, the word line is supplied by the first, higher voltage and the bit line is supplied by a second, lower voltage. During write operations, the write circuit is driven by the first, higher voltage while the bit lines are still at the lower voltage. An SRAM cell, an SRAM array plus a write circuit used to perform the method are also described.

Method to improve performance of SRAM cells, SRAM cell, SRAM array, and write circuit

Asymmetrical random access memory cell () including cross coupled inverters () which are driven at their nodes () by separate bit-lines (blt, blc) of a pair of complementary bit-lines, which are connected via a pass-transistor (), wherein the random access memory cell is asymmetrical by means of the cross coupled inverters () which have asymmetrically physical behaviours whereby different switching thresholds of the inverters are present, and that the pass-transistors () are driven by separate controlled wordlines (wl, wwl).

Asymmetrical random access memory cell, and a memory comprising asymmetrical memory cells

An asymmetrical random access memory cell () including cross coupled inverters () which are driven at their nodes () by separate bit-lines (blt, blc) of a pair of complementary bit-lines, which are connected via a pass-transistors (), wherein said cross coupled inverters () have different switching thresholds and exhibit asymmetrical physical behaviours, wherein an additional pass-transistor () is provided in series to one of the pass-transistors () between one of the nodes () and its dedicated bit-line (blc). Further the invention relates to a random access memory including such memory cells and to a method of operating such a memory.

Asymmetrical random access memory cell, memory comprising asymmetrical memory cells and method to operate such a memory

In a first aspect, a first method is provided for accessing memory. The first method includes the steps of (1) storing a bit in a cell included in a memory having a plurality of cells arranged into rows and columns, wherein each cell includes a group of transistors adapted to both store the bit and affect a signal asserted during a read operation on a bit line coupled to the cell such that the affected signal matches a value of the bit stored in the cell; and (2) preventing the value of the bit stored in the cell from changing state while the group of transistors affects the signal asserted during the read operation on the bit line coupled to the cell. Numerous other aspects are provided.

Methods and apparatus for accessing memory

A pulse to static converter for SRAM in which the converter latch is comprised of two cross-coupled, complementary, FET pairs. The FETs of each pair are coupled drain to drain between a positive voltage source and ground. The output state of SRAM sense amplifier is coupled as an input to the grates of one FET pair and the state established by this input is latched via the cross coupling with the other FET pair.

Output driver with pulse to static converter

A SRAM sense amplifier timing circuit provides various delay settings for the sense amplifier enable signal (sae) and the sense amplifier reset signal (rse) in order to allow critical timing adjustments to be made for early mode, late mode conditions by varying the timing or with of the sense amplifier output pulse. These timing adjustments are programmable using scan in bits.

Programmable sense amplifier timing generator

A device and method for storing information including an array of memory cells organized in bitlines and wordlines. The bitlines are subdivided in sections of wordlines and the sectioned bitlines are connected to a global bitline by a connector. The connector is made bidirectional and uses the high order part of the wordline addresses for this section of bitlines as a disable reset command. The reset stays active for unselected portions, compensating leakage of a mass of unselected cells which could disturb valid read signals.

Device for storing information and a method for partial write and restore

The present invention relates to content addressable memory (CAM), particularly, to a CAM having its memory array, which contains a plurality of memory locations, being divided into at least a first and a second memory block ( ), whereby the first and second memory block ( ) are formed by a first and second portion of each of said memory locations, respectively. The CAM further comprises a first set of compare lines ( ) and a first set-of match lines ( ) associated to said first memory block ( ), and a second set of compare lines ( ) and a second set of match lines ( ) associated to said second memory block ( ), and pre-charge units ( ) for charging said match lines before a comparison operation. The present invention provides an improved CAM which allows flagging of memory locations of which the content only partially matches a given comparison value. This is achieved by a CAM according to the above features using the pre-charge state of the match lines ( ) as a logically valid state.

Content addressable memory

A virtual two-port memory structure with fast write-thru operation is proposed. The virtual two-port memory structure employs a single-port memory cell (200). Means for comparing (260) compare a read address AR with a write address AW and means (270) for writing data from the data input terminal (250) into the cell (200) are bypassing said data to the data output terminal (280) as well, such that a write-thru operation is enabled if the read address AR matches the write address AW. The data just written into the cell are immediately available as read data within the same cycle. The multiplex unit used in prior art solutions is no longer necessary, the delay caused by this device is omitted and the advantages of the virtual two-port cell requiring less chip space are maintained.

Virtual two-port memory structure with fast write-thru operation

Integrated circuit package comprising a power supply distribution wiring and a chip interconnection signal wiring both formed on the top surface of a passive semiconductor interconnection carrier (2) in which a power supply decoupling capacitor is implemented. Spaced wells (4) of a first conductivity type are provided in the surface of said carrier of a second conductivity type. The power supply distribution wiring comprises first and second conductive lines (5,6) within a first wiring level (WL1). Said first conductive lines (5) are deposited on the surface areas of said wells (4) in an ohmic contact relationship and said second conductive lines (6) are deposited on the surface areas of said carrier (2) between said wells (4) in an ohmic contact relationship. Said first and second conductive lines are connected to first and second terminals of the power supply, respectively, so that the junction capacitance between said wells (4) and the carrier material (2) embedding said wells forms said decoupling capacitor. At least one active integrated circuit chip (1) is mounted and electrically connected to the passive semiconductor interconnection carrier (2).

Integrated circuit package

Integrated circuit package comprising a power supply distribution wiring and a chip interconnection signal wiring both formed on the top surface of a passive semiconductor interconnection carrier (2) in which a power supply decoupling capacitor is implemented. Spaced wells (4) of a first conductivity type are provided in the surface of said carrier of a second conductivity type. The power supply distribution wiring comprises first and second conductive lines (5,6) within a first wiring level (WL1). Said first conductive lines (5) are deposited on the surface areas of said wells (4) in an ohmic contact relationship and said second conductive lines (6) are deposited on the surface areas of said carrier (2) between said wells (4) in an ohmic contact relationship. Said first and second conductive lines are connected to first second terminals of the power supply, respectively, so that the junction capacitance between said wells (4) and the carrier material (2) embedding said wells forms said decoupling capacitor. At least one active integrated circuit chip (1) is mounted and electrically connected to the passive semiconductor interconnection carrier (2).

The present invention teaches an arrangement for increasing the output impedance of a power amplifier coupled to a capacitively loaded line during the switching of power levels by the amplifier on the line. The arrangement of the invention reduces undesired noise voltage during switching. The present invention achieves this end by using a control circuit composed of a differential amplifier which has one input fed from the junction of an impedance resistor and a transistor that simulate the power stage transistor in the power amplifier being switched. This control circuit provides control voltage outputs to power control transistors which are connected to and control the speed of the power stage transistors used to change and discharge the capcitively loaded line.

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Altdorf, Germany

Otto M Wagner