Texas Instruments Corporation

Other

Ciclon Semiconductor Device Corp.

Texas Instruments Japan Limited

Osvaldo Jorge Lopez

Jonathan Almeria Noquil

Juan Alejandro Herbsommer

Simon John Molloy

Thomas Eugene Grebs

Tianyi Luo

Marie Denison

Satyendra Singh Chauhan

Brian Ashley Carpenter

David Jauregui

Walter Hans Paul Schroen

Lance Cole Wright

Tom Grebs

Rajen Manicon Murugan

Yiqi Tang

Haian Lin

Makarand Ramkrishna Kulkarni

Liang Wan

Lucian Hriscu

Gerald H Horn

Joseph Maurice Khayat

Bernardo Gallegos

Ubol Udompanyavit

Mark E Granahan

George J Przybylek

R Michael Nelson

Johathan A Noquil

Mark Henry S Antiporta

Fernando V Capinig

Ricky B Calustre

Emmievel S Anacleto

Mizpa B Mijares

In some examples, a semiconductor package comprises a multi-layer package substrate. The multi-layer package substrate includes first and second metal layers, the first metal layer positioned above the second metal layer and coupled to the second metal layer by way of a via. The substrate also includes a dielectric covering at least part of the first and second metal layers and the via. The package includes a plated metal layer plated on at least part of the first metal layer and positioned above the dielectric, a combination of the first metal layer and the plated metal layer being thicker than the second metal layer. The package includes a semiconductor die having a device side, the device side vertically aligned with and coupled to the plated metal layer.

Plated metal layer in power packages

A packaged electronic device includes a stacked configuration of a first semiconductor die in a first recess in a first side of a first conductive plate, a second semiconductor die in a second recess in a first side of a second conductive plate, a third conductive plate electrically coupled to a second side of the second semiconductor die, and a package structure that encloses the first semiconductor die, and the second semiconductor die, where the package structure includes a side that exposes a portion of a second side of the first conductive plate.

Packaged electronic device with film isolated power stack

A semiconductor package comprises a first die thermally coupled to a first thermally conductive device. The first thermally conductive device has a first surface exposed to an exterior of the semiconductor package. The package comprises a second die thermally coupled to a second thermally conductive device, the second thermally conductive device having a second surface exposed to an exterior of the semiconductor package. The first and second dies are positioned in different horizontal planes.

Multi-die package with multiple heat channels

In a described example, an apparatus includes: a package substrate having a planar die mount surface; recesses extending into the planar die mount surface; and a semiconductor device die flip chip mounted to the package substrate on the planar die mount surface, the semiconductor device die having post connects having proximate ends on bond pads on an active surface of the semiconductor device die, and extending to distal ends away from the semiconductor device die having solder bumps, wherein the solder bumps form solder joints to the package substrate within the recesses.

Stress relief for flip-chip packaged devices

A semiconductor package includes a leadframe including a die pad and a plurality of lead terminals. A vertical semiconductor device is attached on a first side by a die attach material to the die pad. A first clip is on the first vertical device that is solder connected to a terminal of the first vertical device on a second side opposite to the first side providing a first solder bonded interface, wherein the first clip is connected to at least a first of the lead terminals. The first solder bonded interface includes a first protruding surface standoff therein that extends from a surface on the second side of the first vertical device to physically contact the first clip.

Semiconductor package with solder standoff

A method of making a semiconductor device includes separating a conductive structure of a leadframe into interior conductive leads using an etching process. The method includes forming a first molded structure by applying a first molding compound to a leadframe having a conductive structure, separating the conductive structure into at least two interior contact portions, attaching a semiconductor die to at least one of the interior contact portions, the at least two interior contact portions being supported by the first molding compound, and forming a second molded structure by applying a second molding compound to at least part of the semiconductor die and at least two interior contact portions.

High I/O density flip-chip QFN

A packaged electronic device includes a semiconductor die, a conductive plate coupled to a lead, a solder structure and a package structure. The semiconductor die has opposite first and second sides and a terminal exposed along the second side. The conductive plate has opposite first and second sides and an indent that extends into the first side, the conductive plate, and the solder structure extends between the second side of the semiconductor die and the first side of the conductive plate to electrically couple the conductive plate to the terminal, and the solder structure extends into the indent. The package structure encloses the semiconductor die, the conductive plate and a portion of the lead.

Conductive plate stress reduction feature

A self-powered electronic system comprises a first chip of single-crystalline semiconductor embedded in a second chip of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container bordered by ridges. The flat side of the slab includes a heavily n-doped region forming a pn-junction with the p-type bulk. A metal-filled deep silicon via through the p-type ridge connects the n-region with the terminal on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.

Photo-sensitive silicon package embedding self-powered electronic system

A power converter () comprising a semiconductor chip () with a first () and a parallel second () surface, and through-silicon vias (TSVs,). The chip embedding a high-side (HS) field-effect transistor (FET) interconnected with a low side (LS) FET. Surface () includes first metallic pads () as inlets of the TSVs, and an attachment site for an integrated circuit (IC) chip (). Surface () includes second metallic pads () as outlets of the TSVs, and third metallic pads as terminals of the converter: Pad () as HS FET inlet, pad () as HS FET gate, pad () as LS FET outlet, pad () as LS FET gate, and gate () as common HS FET and LS FET switch-node. Driver-and-controller IC chip) has the IC terminals connected to respective first pads.

Power converter monolithically integrating transistors, carrier, and components

Disclosed embodiments relate to a semiconductor device. A semiconductor device is fabricated by attachment of a first chip to a first surface of a pad of a leadframe. Each of one or more terminals of the first chip is connected to a respective lead of the leadframe. The first chip and the first surface of the pad are then encapsulated in a packaging material, while leaving an opposite second surface of the pad exposed. A second chip is attached to a recessed portion of the second surface of the pad so that at least one terminal of the second chip is substantially coplanar with an un-recessed portion of the second surface. In one embodiment, a third chip is also attached to the recessed portion of the second surface so that at least one terminal of the third chip is substantially coplanar with the un-recessed portion of the second surface.

Semiconductor device having terminals directly attachable to circuit board

A self-powered electronic system comprises a first chip () of single-crystalline semiconductor embedded in a second chip () of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container () bordered by ridges (). The flat side () of the slab includes a heavily n-doped region () forming a pn-junction () with the p-type bulk. A metal-filled deep silicon via () through the p-type ridge () connects the n-region with the terminal () on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.

Growing community of inventors

Annandale, NJ, United States of America

Osvaldo Jorge Lopez