Renesas Electronics Corporation

Kabushiki Kaisha Toshiba

Renesas Technology Corp.

Panasonic Corporation

Fujitsu Semiconductor Limited

Fujitsu Microelectronics Limited

Original Engineering Consultants Co., Ltd.

Osamu Suga

Tsuneo Terasawa

Toshihiko Tanaka

Takashi Kamo

Daisuke Kondo

Kazuyuki Sakata

Yusaku Ono

Hajime Aoyama

Hirofumi Taguchi

Yushi Okuno

Toshiaki Sugioka

Hiroyuki Shigemura

There is provided a method of high-sensitively detecting both of a phase defect existing in a mask blank and a phase defect remaining after manufacturing an EUVL mask. When the mask blank is inspected, EUV light having illumination NA to be within an inner NA but a larger value is irradiated. When the EUVL mask is inspected, by using a dark-field imaging optical system including a center shielding portion for shielding EUV light and a linear shielding portion for shielding the EUV light whose width is smaller than a diameter of the center shielding portion, the center shielding portion and the linear shielding portion being included in a pupil plane, the EUV light having illumination NA as large as or smaller than the width of the linear shielding portion is irradiated.

Method of inspecting mask, mask inspection device, and method of manufacturing mask

A inspection image data of the chip A is captured and the data representing the amount of correction of flare corresponded to the chip A is appropriately loaded from the map storage block. Next, a inspection image of the chip A' is captured, and the data representing the amount of correction of flare corresponded to the chip A&#x2032; is loaded from the flare map storage block as the amount of shifting of the edge of the contour of the pattern. The amount of correction is converted, by a correction data generation block which is a correction data generator, into the amount of geometrical correction of pattern which provides correction data. In the comparison block, the images of the geometry of two chips are compared and corrected on the amount of correction of flare generated by a correction data generation block, to thereby judge whether defect is found or not.

Method of inspecting mask pattern and mask pattern inspection apparatus

A reflection-type exposure mask includes a multilayer reflective film in a main surface and serving as a high reflective region to an exposure light, and an absorber pattern on the multilayer reflective film and serving as a low reflective region to the exposure light, wherein a phase difference between reflection lights of the exposure light from the multilayer reflective film and the absorber pattern is in a range of 180&#xb0;&#xb1;10&#xb0;, and the absorber pattern includes first and second linear patterns having longitudinal directions intersecting at right angles, contrast values of optical images of the first and second linear patterns formed on a wafer is to be 0.6 or more when one of the longitudinal directions of the first and second patterns agree with an incident direction of the exposure light to the main surface viewed from above the main surface.

Reflection-type exposure mask and method of manufacturing a semiconductor device

A reflective-type mask having a main surface including a pattern region in the main surface, the pattern region including a multilayer reflective film which reflects the exposure light and a first absorber pattern on the multilayer reflective film, the first absorber pattern including a pattern which absorbs the exposure light and corresponds to a pattern to be formed on a wafer, a light shielding region in the main surface for preventing a region on the wafer excluding a predetermined region from being irradiated with the exposure light when the main surface is irradiated with the exposure light for transferring the first absorber pattern to the predetermined region, the light shielding region including a second absorber pattern having a lower reflectivity to the exposure light than the first absorber pattern and being provided in a position differing from a position in which the first absorber pattern is provided.

Reflective-type mask

According to the present invention, a method for designing a semiconductor integrated circuit layout comprises the steps of: arranging basic logic cells which are circuit patterns corresponding to logic components of a semiconductor integrated circuit; arranging wiring between the basic logic cells; searching for a blank area in which none of the basic logic cells is arranged; extracting a rectangular region from the blank area; if the rectangular region is larger than a specified size, arranging fill cells in the rectangular region according to a predetermined rule and grouping the fill cells into pseudo-hierarchical cells according to a predetermined rule to form a hierarchy; arranging fill cells in the remaining blank areas; and performing optical proximity effect correction on the semiconductor integrated circuit pattern.

Method for designing a semiconductor integrated circuit layout capable of reducing the processing time for optical proximity effect correction

3-D structure design system and method thereof capable of preparing drawings and performing quantity calculation at the same time, and largely eliminating troubles caused when designing a concrete structure by handling the design of concrete-made structures with a cubic 3-D data from the very beginning. The system comprising: data input device for inputting structure data; 3-D structural data search device for searching data on a portion between members and data on a connection between members on the basis of the input data on the concrete-made structure, checking an interference portion between members, aligning members through the result of rivaling between members, automatically adjusting the overlapping of members, and searching the input data on members as data conforming to the concrete structure; body quantities search device for calculation; and result display device for displaying/outputting a search result.

3-D structure design system, a method for designing 3-D structure and a recording medium readable by a computer having a program allowing the computer to execute the method recorded therein

Growing community of inventors

Tokyo, Japan

Osamu Suga