Kabushiki Kaisha Toshiba

Osamu Nagao

Hitoshi Shiga

Ayako Yamano

Koichi Fukuda

Toshiaki Edahiro

Hideo Mukai

Teruo Takagiwa

Yasuyuki Fukuda

Rieko Funatsuki

Akihiro Imamoto

According to one embodiment, a semiconductor memory device includes a plurality of blocks in a memory cell, each of the blocks acting as an erasure unit of data, the block including a plurality of pages, each of the pages including a plurality of memory cell transistors, each of the memory cell transistors being configured to be an erasure state or a first retention state based on a threshold voltage of the memory cell transistor, and a controller searching data in the block with respect to, writing a first flag denoting effective into a prescribed page of the block with the erasure state, and writing the first flag denoting non-effective into a prescribed page of the block with the first retention state, reading out the prescribed page of the block with the first retention state, and determining that the block is writable when the first flag denotes effective.

Semiconductor memory device and method for writing therein

A memory includes memory cells and a sense amplifier including a sense node that transmits a voltage according to a current flowing in one of the memory cells and detects logic of data based on the voltage of the sense node. A write sequence of writing data in a selected cell is performed by repeating write loops each including a write stage of writing data in the selected cell and a verify read stage of verifying that the data has been written in the selected cell by performing discharge from the sense node through the selected cell. The sense amplifier changes, according to a logic of data detected at the verify read stage in a first write loop, a period of discharge from the sense node to the selected cell at the verify read stage in a second write loop following the first write loop.

Semiconductor storage device

A nonvolatile semiconductor storage device according to an embodiment includes an erase circuit executing an erase sequence, wherein in the erase sequence, the erase circuit executes: an erase operation to change a selection memory cell group to an erased state, after the erase operation, a soft program operation on the selection memory cell group to solve over-erased state, and after the soft program operation, a first soft program verification operation performed on at least one partial selection memory cell group of a first partial selection memory cell group and a second partial selection memory cell group so as to confirm whether the partial selection memory cell group includes a predetermined number of memory cells or more that have threshold values equal to or more than a predetermined first threshold value, and after the first soft program verification operation.

Nonvolatile semiconductor storage device

A NAND type flash memory for erasing data every block including plural memory cell transistors that are provided every block and have floating gates formed through first gate insulating film above a well formed in a semiconductor substrate and control gates formed through second gate insulating film above the floating gates, data in the memory cell transistors being rewritable by controlling charge amounts accumulated in the floating gates, and a row decoder having a plurality of MOS transistors having drains that are respectively connected to corresponding word lines connected to the control gates of the plurality of memory cell transistors, the row decoder controlling gate and source voltages of the MOS transistors.

Semiconductor memory device

According to one embodiment, a nonvolatile semiconductor memory includes memory cells storing data of multi-level, a bit scan circuit to scan the number of to-be-written memory cells and the number of memory cells that have passed the verify, a processing unit to perform an operation process based on a scan result of the bit scan circuit, and a control circuit to control an operation of writing data according to a first mode in which a voltage used for an upper-data writing is calculated during a lower-data writing and a second mode used a voltage based on setting information. The bit scan circuit scans the number of to-be-written memory cells before starting writing and the processing unit compares the number of to-be-written memory cells with a criterion and determines one of the first and second modes for the writing based on a result of comparison.

Nonvolatile semiconductor memory and control method thereof

A nonvolatile semiconductor memory device according to one aspect of the present invention includes: a memory cell array provided to perform programming in page units; and a control circuit provided to control the programming. The control circuit includes: means that performs a first detection for memory cells in a part provided as a unit smaller than a page, concurrently with programming to memory cells to be written in a page; and means that subjects the memory cells in the page to a second detection that takes into consideration a failure relief due to a redundant region, when the number of memory cells of unwritten state in the part as detected by the first detection becomes equal to or less than a first constant, and that ends the program operation when the number of memory cells of unwritten state in the page becomes equal to or less than a second constant.

Nonvolatile semiconductor memory device

In a control order of non-selected blocks at the time of data erase operation of one or a plurality of blocks, the control gate line is controlled to ground potential at first, then subsequently, a transfer transistor of the non-selected blocks is set to be an off-state. Next, high voltage is supplied to the well region and the data of the selected block is erased. Then, the control gate line is charged to the voltage which is used, for instance, at the time of reading out, or to the voltage (Vcg) which is used at the verification (Vcg). After the control gate line is charged to Vcg, the erase voltage supplied to the well region is discharged. Then, the control gate line is returned to ground potential after completing the discharge of the well region, and thus the data erase operation of the block is completed.

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Kanagawa-ken, Japan

Osamu Nagao