Hitachi, Ltd.

Hitachi Maxell, Limited

Hitachi Microcomputer Eng. Ltd.

Hitachi Vlsi Engineering Corp.

Hitachi, Vlsi Eng. Corp.

Hitachi Microcomputer Hitachi, Ltd. & Engineering, Ltd.

Osamu Minato

Toshiaki Masuhara

Yoshio Sakai

Katsuhiro Shimohigashi

Toshiaki Yamanaka

Satoshi Meguro

Koichiro Ishibashi

Toshio Sasaki

Naotaka Hashimoto

Norio Suzuki

Takashi Hashimoto

Makoto Motoyoshi

Kiyofumi Uchibori

Toru Kaga

Atsuyoshi Koike

Nobuyuki Moriwaki

Shigeru Honjou

Shigeru Honjyo

Yoshifumi Kawamoto

Hideo Sunami

Shoji Hanamura

Tokuo Kure

Masaharu Kubo

Shinji Shimizu

Masanobu Miyao

Hideaki Nakamura

Mitsumasa Koyanagi

Masashi Horiguchi

Masakazu Aoki

Isao Yoshida

Hiroo Masuda

Eiji Takeda

Katsuki Miyauchi

Kouichi Nagasawa

Kotaro Nishimura

Makoto Saeki

Tokumasa Yasui

Sho Yamamoto

Masaaki Kubotera

Yasuo Yoshitomi

Shigeru Honjiyo

Kiyoo Itoh

Shuji Ikeda

Kazuo Yano

Yoshinobu Nakagome

Ryoichi Hori

Akihiro Shimizu

Jun Etoh

Hideo Nakamura

Makoto Ohkura

Yuji Yatsuda

Yoshiaki Kamigaki

Yasuo Wada

Shinya Ohba

Shinpei Iijima

Yoshimune Hagiwara

Tetsuya Nakagawa

Minoru Nagata

Tetsuya Hayashida

Takahiro Okabe

Katsuro Sasaki

Shinichi Ikenaga

Hideaki Kato

Tetsuichi Kudo

Hisao Katto

Takashi Nishida

Masaaki Nakai

Katsuaki Takagi

Norikazu Hashimoto

Nobuyoshi Tanimura

Takeaki Okabe

Yoshio Uetani

Mineo Katsueda

Takashi Tokuyama

Kazutoshi Ashikawa

Shigeru Honjo

Mitsuo Ito

Shin-ichi Muramatsu

Kiyotsugu Ueda

Shigeo Ohtaka

Akihiro Tomozawa

Hirotsugu Kozuka

Tamura Hiroshi

Tamura Masao

Yukio Sasaki

Fumio Kojima

The manufacture of a memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. The manufacture of each load MISFET consists of forming source, drain and channel regions within the same polycrystalline silicon film, and a gate electrode consisting of a different layer conductive film, such as a polycrystalline film, than that of the drive MISFETs. The manufacture of the memory cell having such a stacked arrangement, facilitates the patterning of the source (drain) region and gate electrode of each load MISFET thereof to have an overlapping relationship with each other so as to increase the effective capacitance associated with each of the memory cell storage nodes. The gate electrodes of both the drive and load MISFETs are formed of n-type or of n-type and p-type polycrystalline silicon films, respectively, and electrical connections are formed between the drain regions of the first and second p-channel load MISFETs with that of the drain regions of the first and second n-channel drive MISFETs through separate polycrystalline silicon films, respectively. Also, there are formed electrical connections between the polycrystalline silicon gate electrodes of the first and second load MISFETs with that of drain regions of the second and first drive MISFETs, through the poly-Si gate electrodes of the first and second drive MISFETs, in each memory cell of the SRAM, respectively, furthermore.

Semiconductor integrated circuit device

A memory cell of the type a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETS. Each load MISFET of a memory cell consists of a source, drain and channel region formed within the same polycrystalline silicon film, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. In a memory cell having such a stacked arrangement, the source (drain) region and gate electrode of each load MISFET thereof are patterned to have an overlapping relationship with each other so as to increase the effective capacitance associated with each of the memory cell storage nodes. The gate electrodes of both the drive and load MISFETs are formed of n-type and p-type polycrystalline silicon films, respectively, and the drain regions of the first and second p-channel load MISFETs are electrically connected to the drain regions of the first and second n-channel drive MISFETs through separate polycrystalline silicon films, respectively. The polycrystalline silicon gate electrodes of the first and second load MISFETs are respectively electrically connected to the drain regions of the second and first drive MISFETs in each memory cell of the SRAM, furthermore.

A memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. Each load MISFET of a memory cell consists of a source, drain and channel region formed of a semiconductor strip, such as a polycrystalline silicon film strip, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. In a memory cell having such a stacked arrangement, the source region and gate electrode of each load MISFET thereof are patterned to have a widely overlapping relationship with each other to form a capacitor element thereacross such that an increase in the overall capacitance associated with each of the memory cell storage nodes is effected thereby decreasing occurrence of soft error. The overlapping relationship for effecting the large capacitor element across the source and gate of the respective load MISFETs is provided by an ion implanting scheme of a p-type impurity into the semiconductor strip. A separate mask for ion-implantation for the formation of the source region of the load MISFET is added followed by the addition of the gate electrode thereof in a manner so as to have a widely overlapping relationship with that of the source region.

A memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is provided in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. Each load MISFET of a memory cell consists of a source, drain and channel region formed of a semiconductor strip, such as a polycrystalline silicon film strip, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. A wiring line, formed as a separate conductive layer, is provided in the stacking arrangement of the drive and load MISFETs of a memory cell for applying a ground potential to source regions of the drive MISFETs thereof.

A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.

Semiconductor memory

In a memory cell of SRAM of CMOS type, load MISFET having a polycrystalline silicon film as area of source, drain and channel is stacked on drive MISFET, and gate electrodes of the drive MISFET and the load MISFET are constituted by conductive films in different layers. Area of source and drain provided on the polycrystalline silicon film has an overlapped area with the gate electrode of the load MISFET.

A static RAM memory is divided into a plurality of mats (12). Word lines (16) in each pair of mats are accessed by an x-decoder (14). Columns or bit lines are accessed by a y-decoder (20) which selectively connect pairs of bit lines (22) to common data bus segments (24). Transistors (60, 62) connect selected bit lines with a load during a write cycle to stabilize those bit lines and memory cells into which data is written. The x-decoders are connected with near word lines (16a) for addressing a near half of each mat and are operatively connected with remote word lines (16b) for addressing word lines in a remote half of each mat. In this manner, each mat is divided into two effective mats. The bit lines of all the effective mats within an actual mat are connected with the same output data bus segment. A pair of sensing amplifiers (32) is provided for each bit of memory which is accessed concurrently, e.g. eight bits, such that the high and low output of each flip-flop memory cell (18) are both amplified. A pair of driving amplifiers (34) further amplify each high and low output before applying them to an output data bus (38).

Semiconductor memory with divided bit load and data bus lines

A logic circuit includes first, second, third, fourth, fifth and sixth field effect transistors or FETs, input nodes and an output node. The fifth and sixth FETs are connected to the output node. The first and third FETs are connected to the fifth FET. The second and fourth FETs are connected to the sixth FET. The first and second FETs are connected to the first input node. The third and fourth FETs are connected to the second node. A first signal is supplied to the first input node. A second signal is supplied to gate electrodes of the first and fourth FETs. A signal having a phase opposite to the second signal is supplied to gate electrodes of the second and third FETs. A third signal is supplied to the second input node. One signal selected from the first, second and the third signals is supplied to the gate electrode of the fifth FET. A signal having a phase opposite to the signal supplied to the gate electrode of the fifth FET is supplied to the gate electrode of the sixth FET. An output signal related to the first, second and third input signals is generated from the output node. The output signal is, for example, a carry output signal or alternatively a majority decision logic output signal.

Logic circuit and data processing apparatus using the same

A semiconductor static random access memory having a high .alpha.-ray immunity and a high packing density is provided which is also capable of high-speed operation. A semiconductor memory device comprises static random access memory cells each including a flip-flop circuit. Storage nodes of each flip-flop circuit have respective pn-junctions formed at regions sandwiched between gate electrodes of first insulated gate field effect transistors and gate electrodes of second insulated gate field effect transistors, respectively. The pn-junction has an area smaller than that of a channel portion of the first or second insulated gate field effect transistor. The gate electrode of one of the two first insulated gate field effect transistors and the drain region of the other insulated gate field effect transistor, on one hand, and the drain region of the one insulated gate field effect transistor and the gate electrode of the other insulated gate field effect transistor, on the other hand, are electrically cross-coupled mutually through first and second electrically conductive films, respectively. Also, to increase packing density and enhance immunity to soft error, the gate electrodes of the first and second insulated gate field effect transistors extend substantially in parallel with one another and the channel regions of the first and second insulated gate field effect transistors extend substantially in parallel with one another.

Semiconductor memory device having flip-flop circuits

Herein disclosed is a semiconductor integrated circuit device having a SRAM, in which two MISFETs of a flip-flop circuit of a memory cell are connected directly with an n.sup.+ -type drain region so that they are cross coupled; and in which a p.sup.+ -type semiconductor region is formed below a direct contact part by making use of the mask used in the step of forming contact holes for the direct contact part. The p.sup.+ -type semiconductor region aids as a barrier to prevent soft errors of the SRAM due to .alpha.-particles.

Semiconductor integrated circuit device and process for fabricating the

Disclosed is an MOSIC including a plurality of silicon gate type MOSFET's in which, after polycrystalline silicon wirings are formed simultaneously with polycrystalline silicon gates, the electrodes contacted with the source and drain regions are made of polycrystalline silicon so as to be connected to the polycrystalline silicon wirings, thereby to prevent the shallow pn junctions of the source and drain regions from being destroyed by the contacts and to provide a high degree of integration to one silicon chip.

Semiconductor devices and a process for producing the same

A semiconductor integrated circuit includes: a data output terminal; a first semiconductor element connected between a first operating potential point and the data output terminal; a second semiconductor element connected between the data output terminal and a second operating potential point; first control means connected to a control input terminal of the first semiconductor element; second control means connected to a control input terminal of the second semiconductor element; first generating means for generating a first predetermined voltage; and second generating means for generating a second predetermined voltage higher than the first predetermined voltage. When voltage at the data output terminal is higher than the second predetermined voltage, the first control means controls the first semiconductor element to be in the OFF-state, and the second control means controls the second semiconductor element to be in the ON-state to lower the voltage of the data output terminal to the second predetermined voltage. On the other hand, in the case where the voltage of the data output terminal is lower than that of the first predetermined voltage, the output of the first control means controls the first semiconductor element so that it is in the ON-state and the output of the second control means controls the second semiconductor element so that it is in the OFF-state so as to raise the voltage of the data output terminal to the first predetermined voltage.

High speed MOSFET output buffer with low noise

A semiconductor memory device is disclosed, in which a word line address translation unit, a data line address translation unit, a first spare memory and a second spare memory are provided in addition to a main memory to relieve a defective memory cell in the main memory. Spare word line address signals for selecting a spare word line on the first spare memory are written in the word line address translation unit, spare data line address signals for selecting a spare data line on the second spare memory are written in the data line address translation unit, and each of the word line address translation unit and the data line address translation unit is constructed of an ordinary semiconductor memory of the multi-bit output type.

Semiconductor memory device

Growing community of inventors

Tokyo, Japan

Osamu Minato