Stmicroelectronics S.r.l.

Other

Ovonyx Inc.

Hynix Semiconductor Inc.

Osama Khouri

Rino Micheloni

Guido Torelli

Andrea Sacco

Andrea Pierin

Stefano Gregori

Ilaria Motta

Fabio Pellizzer

Ferdinando Bedeschi

Claudio Resta

Stefano Zanardi

Giulio Martinozzi

Carlo Caimi

Giorgio Pollaccia

Giovanni Mastrodomenico

Dario Soltesz

Daniele Vimercati

Giovanni Campardo

Roberto Ravasio

Massimiliano Picca

Alessandro Manstretta

Paolo Caprara

Giancarlo Ragone

Miriam Sangalli

Giorgio Bosisio

Sara Fiorina

A contact structure for a PCM device is formed by an elongated formation having a longitudinal extension parallel to the upper surface of the body and an end face extending in a vertical plane. The end face is in contact with a bottom portion of an active region of chalcogenic material so that the dimensions of the contact area defined by the end face are determined by the thickness of the elongated formation and by the width thereof.

Sublithographic contact structure, in particular for a phase change memory cell, and fabrication process thereof

A flash NAND electronic memory device includes non-volatile cells having a high integration density and a relative programming method. The memory device is integrated on a semiconductor substrate and includes a matrix with word lines and bit lines organized in sectors of memory cells. The memory device is between the cells of the opposite word lines belonging to at least one of the sectors of the matrix. A lateral coating along the direction of the bit lines has at least one conductive layer with a contact terminal being selectively biased or left floating during each program, read or erase operation. Each cell belongs to a sector.

Electronic memory device having high integration density non-volatile memory cells and a reduced capacitive coupling

A method of distributing an electric quantity through an electronic circuit for local exploitation by at least one circuit block of the electronic circuit that includes providing in the electronic circuit first and second conductive lines, the first conductive line distributing a first electric potential and the second conductive line carrying a second electric potential that is a dedicated reference electric potential for the first electric potential, the first and second electric potentials corresponding to the distributed electric quantity, and locally exploiting the distributed electric quantity by at least one circuit block of the electronic circuit, by locally reconstructing the distributed electric quantity from the first and second electric potentials without perturbing them, particularly without either sinking or injecting any significant current from or into the first and second conductive lines.

Distribution of an electric quantity through a circuit

A method is provided for transferring data in a memory that includes memory cells forming memory pages, and a page buffer that includes a register, with signal lines selectively transferring data stored in the register to the memory cells of a selected one of the memory pages and an output interface of the memory. Data read from or to be written to the memory cells of the selected one of the memory pages is at least temporarily stored in the register, and outputs of the register are buffered so as to decouple the outputs of the register from the signal lines. The signal lines include bitlines that are each coupled to some of the memory cells and data lines that are coupled to the output interface of the memory. The buffering comprises selectively driving the bitlines or the data lines according to a data word that is stored in the register.

Method of transferring data in an electrically programmable memory

A phase change memory has an array formed by a plurality of cells, each including a memory element of calcogenic material and a selection element connected in series to the memory element; a plurality of address lines connected to the cells; a write stage and a reading stage connected to the array. The write stage is formed by current generators, which supply preset currents to the selected cells so as to modify the resistance of the memory element. Reading takes place in voltage, by appropriately biasing the selected cell and comparing the current flowing therein with a reference value.

Method of writing to a phase change memory device

An electronic memory device with a high density of non-volatile memory cells has a reduced capacitance cell-to-cell interference. The memory cells are integrated on a semiconductor substrate and are organized in a matrix of cells with word lines and bit lines connected to the cells. Each memory cell includes at least one floating gate transistor having a floating gate region projecting from the substrate, and a control gate region capacitively coupled to the floating gate region. Between the cells of opposite word lines, a lateral coating is provided that includes at least one conductive layer floating along the direction of the bit lines.

Electronic memory device having high density non-volatile memory cells and a reduced capacitive interference cell-to-cell

A page buffer is provided for an electrically programmable memory that includes multiple memory cells forming multiple memory pages. The page buffer includes a register for at least temporarily storing data read from or to be written to the memory cells of a selected memory page. The register includes multiple latches and multiple buffer elements. Each of the latches is coupled to at least one signal line for transferring the data bit that is stored in the latch. Each of the buffer elements decouples an output of a corresponding one of the latches from the signal line, with the buffer element driving the signal line according to the data bit stored in the corresponding latch. Also provided is a method of transferring data from a register to signal lines in an electrically programmable memory.

Page buffer for a programmable memory device

A circuit for converting a direct current input voltage into an output voltage greater than the input voltage. The circuit includes a charge pump and a block for generating pulse signals of a predetermined frequency to be applied to a control input of the charge pump. The settling time, i.e. the time necessary for the output voltage to attain its operating value and to maintain it with a given precision, is reduced by providing the circuit with charge injection control via modulation of the duty cycle of the pulse signals as a function of the difference between the output voltage, or a predetermined fraction thereof, and a predetermined reference voltage and in such a manner as to reduce the settling time as the difference diminishes. The circuit includes a regulator that controls the charge pump based upon the predetermined reference voltage.

Charge pump circuit with a brief settling time and high output voltage regulation precision

Phase change memory device

The device includes a circuit for sector remapping having a CAM (Content Addressable Memory) unit, associated to and in data communication with a multiplexer unit. The CAM unit detects that a sector is defective, it provides the pre-programmed address of a replacing sector and it activates the multiplexer which performs the replacement. The defective sectors and the corresponding locations of the address map are therefore advantageously positioned to the rear to the addressing area. The addressing area is consequently continuous, thus allowing the information to be easily stored and retrieved.

Non volatile memory device including a predetermined number of sectors

A phase change memory includes a temperature sensor having a resistance variable with temperature with the same law as a phase-change storage element. The temperature sensor is formed by a resistor of chalcogenic material furnishing an electrical quantity that reproduces the relationship between the resistance of a phase change memory cell and temperature; the electrical quantity is processed so as to generate reference quantities as necessary for writing and reading the memory cells. The chalcogenic resistor has the same structure as a memory cell and is programmed with precision, preferably in the reset state.

Circuit and method for temperature tracing of devices including an element of chalcogenic material, in particular phase change memory devices

The phase-change nonvolatile memory array is formed by a plurality of memory cells extending in a first and in a second direction orthogonal to each other. A plurality of column-selection lines extend parallel to the first direction. A plurality of word-selection lines extend parallel to the second direction. Each memory cell includes a PCM storage element and a selection transistor. A first terminal of the selection transistor is connected to a first terminal of the PCM storage element, and the control terminal of the selection transistor is connected to a respective word-selection line. A second terminal of the PCM storage element is connected to a respective column-selection line, and a second terminal of the selection transistor is connected to a reference-potential region while reading and programming the memory cells.

Architecture of a phase-change nonvolatile memory array

A charge pump circuit, connected between a first voltage reference and an output terminal, comprises at least two parallel-coupled stages having an elementary charge pump circuit connected between said first voltage reference and said output terminal, and adjustment circuitry connected between said output terminal and respective control terminals of said at least two stages. This adjustment circuitry is arranged to select for actuation an appropriate combination of these elementary stages according to the current absorbed from a load connected to the output terminal.

Low power charge pump circuit

A method for programming a nonvolatile memory cell envisages applying in succession, to the gate terminal of the memory cell, a first and a second programming pulse trains with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next in the first programming pulse train is greater than the amplitude increment between one pulse and the next in the second programming pulse train. The programming method envisages applying, to the gate terminal of the memory cell and before the first programming pulse train, a third programming pulse train with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next may be less than the amplitude increment in the first programming pulse train and substantially equal to the amplitude increment in the second programming pulse train, or else may be greater than the amplitude increment in the first programming pulse train.

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Milan, Italy

Osama Khouri