Motorola Corporation

Other

International Business Machines Corporation

The United States of America as Represented by the United States

Lockheed Martin Energy Systems, Inc.

Orin W Holland

John R Alvis

James R Pfiester

Devendra K Sadana

Darrell Keith Thomas

Syd R Wilson

Thomas Allen Wetteroth

Clark W White

Richard B Gregory

Raymond A Zuhr

Dariush Fathy

Dashun Zhou

Systems and methods are described for transfer of a thin-film via implantation, wafer bonding, and separation. A method for transfer of a thin-film, includes: implanting a source crystal with ions along a crystallographic channel and at a temperature of at least approximately 200&deg; C. to i) form a strained region and ii) define the thin-film; then bonding a surface of the thin-film to a target wafer; and then separating a) the target wafer and the thin-film from b) a remainder of the source crystal along the strained region. The systems and methods provide advantages because the electrical carriers in the crystal, and consequently the thin-film, are not deactivated and the quality of the transferred thin-film is improved.

Method for transfer of thin-film of silicon carbide via implantation and wafer bonding

A process for forming Silicon-On-Insulator is described incorporating the steps of ion implantation of oxygen into a silicon substrate at elevated temperature, ion implanting oxygen at a temperature below 200&deg; C. at a lower dose to form an amorphous silicon layer, and annealing steps to form a mixture of defective single crystal silicon and polycrystalline silicon or polycrystalline silicon alone and then silicon oxide from the amorphous silicon layer to form a continuous silicon oxide layer below the surface of the silicon substrate to provide an isolated superficial layer of silicon. The invention overcomes the problem of buried isolated islands of silicon oxide forming a discontinuous buried oxide layer.

Buried oxide layer in silicon

A process for forming Silicon-On-Insulator is described incorporating the steps of ion implantation of oxygen into a silicon substrate at elevated temperature, ion implanting oxygen at a temperature below 200.degree. C. at a lower dose to form an amorphous silicon layer, and annealing steps to form a mixture of defective single crystal silicon and polycrystalline silicon or polycrystalline silicon alone and then silicon oxide from the amorphous silicon layer to form a continuous silicon oxide layer below the surface of the silicon substrate to provide an isolated superficial layer of silicon. The invention overcomes the problem of buried isolated islands of silicon oxide forming a discontinuous buried oxide layer.

Method of forming buried oxide layers in silicon

A method for preparing a silicon-on-insulator material having a relatively defect-free Si overlayer involves the implanting of oxygen ions within a silicon body and the interruption of the oxygen-implanting step to implant Si ions within the silicon body. The implanting of the oxygen ions develops an oxide layer beneath the surface of the silicon body, and the Si ions introduced by the Si ion-implanting step relieves strain which is developed in the Si overlayer during the implanting step without the need for any intervening annealing step. By relieving the strain in this manner, the likelihood of the formation of strain-induced defects in the Si overlayer is reduced. In addition, the method can be carried out at lower processing temperatures than have heretofore been used with SIMOX processes of the prior art. The principles of the invention can also be used to relieve negative strain which has been induced in a silicon body of relatively ordered lattice structure.

Processing method for forming dislocation-free SOI and other materials

Metal-oxide-semiconductor (MOS) transistors with n-type source/drain regions also having germanium-doped regions in or near the source/drains. The presence of germanium near or at the location of phosphorus in graded source drains (GSDs), lightly doped drains (LDDs) and double diffused drains (DDDs) gives a better profile of the drain region with a reduced junction depth than that obtainable with phosphorus or particularly phosphorus and arsenic together. Good grading of the drain junction to avoid hot carrier instability or hot carrier injection problems is obtained along with shallow source junctions, which minimizes lateral dopant diffusion and decreases the distance between n.sup.- and n.sup.+ regions in GSDs and LDDs.

N-channel MOS transistors having source/drain regions with germanium

A method for enhancing the conversion of Si to SiO.sub.2 in a directional fashion wherein steam or wet oxidation of Si is enhanced by the prior implantation of Ge into the Si. The unique advantages of the Ge impurity include the directional enhancement of oxidation and the reduction in thermal budget, while at the same time, Ge is an electrically inactive impurity.

Method for enhancing growth of SiO.sub.2 in Si by the implantation of

Metallic silicide films are formed on silicon substrates by contacting the substrates with a low-energy ion beam of metal ions while moderately heating the substrate. The heating of the substrate provides for the diffusion of silicon atoms through the film as it is being formed to the surface of the film for interaction with the metal ions as they contact the diffused silicon. The metallic silicide films provided by the present invention are contaminant free, of uniform stoichiometry, large grain size, and exhibit low resistivity values which are of particular usefulness for integrated circuit production.

Method for forming metallic silicide films on silicon substrates by ion

Metal-oxide-semiconductor (MOS) transistors with n-type source/drain regions also having germanium-doped regions in or near the source/drains. The presence of germanium near or at the location of phosphorus in graded source drains (GSDs), lightly doped drains (LDDs) and double diffused drains (DDDs) gives a better profile of the drain region with a reduced junction depth than that obtainable with phosphorus or particularly phosphorus and arsenic together. Good grading of the drain junction to avoid hot carrier instability or hot carrier injection problems is obtained along with shallow source junctions, which minimizes lateral dopant diffusion and decreases the distance between n- and n+ regions in GSDs and LDDs.

An improved process is disclosed for forming the field oxide which provides isolation between adjacent devices in an integrated circuit. In one embodiment of the invention the improvement includes implanting halogen ions, and preferably chlorine ions, into the selected regions of a semiconductor substrate where field oxide is to be formed. The halogen ions are implanted before the field oxide is thermally grown and result in a localized enhancement of the oxide growth rate in the vertical direction compared to the lateral direction. For a given oxidation cycle, the halogen implant results in the growth of a thicker oxide with minimum lateral encroachment.

Isolation process for semiconductor devices

A process is disclosed for controlling the surface doping of two regions of a semiconductor device and more specifically for using such control to achieve the necessary field doping in a CMOS device structure. In accordance with one embodiment of the invention a silicon substrate is provided which has first and second regions of opposite conductivity type. A uniform doping such as by ion implantation is provided into each of the conductivity regions. The two regions or portions thereof are then simultaneously differently oxidized to cause a differential segregation of the dopant into the thermally grown oxide. The differential oxide growth can be achieved by selectively implanting halogen ions into the wafer surface prior to the thermal oxidation.

Process of controlling surface doping

A complementary metal-oxide-semiconductor (CMOS) isolation structure where the field isolation structure between the adjacent areas of different conductivity types has a channel stop doped with boron or phosphorus affected by germanium. The dual use of germanium and a second dopant selected from the group of phosphorus and boron provides a more precisely placed channel stop, since the germanium retards the diffusion of the boron and phosphorus and surprisingly provides improved width effect for the devices in the well where the channel stop is employed. Alternatively, the germanium may be placed in such a manner as to avoid retarding absorption of boron or phosphorus into the field oxide and retard its diffusion over the well of a different conductivity type where it is not desired.

Field implant process for CMOS using germanium

A technique for suppressing hillock growth in metal films on integrated circuits through multiple thermal cycles by argon implantation. Although it was known that ion implantation of many species such as arsenic suppressed the growth of hillocks in metal films through one thermal cycle, it was discovered that only one of the proposed ions, argon, would suppress hillock formation for multiple subsequent thermal cycles. For the other species, hillock formation would reoccur after multiple cycles. This characteristic is important for double layer metal (DLM) processes to prevent interlayer shorting.

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Oak Ridge, TN, United States of America

Orin W Holland