Freescale Semiconductor,inc.

On Lok Chau

Hei Ming Shiu

Gor Amie Lai

Lan Chu Tan

Heng Keong Yip

Fei Ying Wong

Thoon Khin Chang

A method for forming reinforced interconnects or bumps on a substrate includes first forming a support structure on the substrate. A substantially filled capsule is then formed around the support structure to form an interconnect. The interconnect can reach a height of up to 300 microns.

Method for forming reinforced interconnects on a substrate

A method for forming multi-layer bumps on a substrate includes depositing an adhesive or a flux on the substrate, depositing a first metal powder on the adhesive, and melting or reflowing the adhesive and first metal powder to form first bumps. An adhesive or a flux and a second metal powder are then deposited on the first bumps, and melted to form second bumps on the first bumps to form multi-layer bumps. The multi-layer bumps are formed without the need for any wet chemicals.

Method for forming multi-layer bumps on a substrate

A method for forming multi-layer bumps on a substrate includes depositing a first metal powder on the substrate, and selectively melting or reflowing a portion of the first metal powder to form first bumps. A second metal powder is then deposited on the first bumps, and melted to form second bumps on the first bumps. A masking plate is disposed over the substrate to select the portions of the metal powders that are melted and the metal powders are melted via an irradiation beam. The multi-layer bump is formed without the need for any wet chemicals.

An electronic device () including a first integrated circuit (IC) die () electrically connected to a first lead frame () and a second IC die () electrically connected to a second lead frame (). The first lead frame () is electrically connected to the second lead frame () by at least one stud bump (), which is selectively formed where an electrical connection between the first lead frame () and the second lead frame () is required. The first and second lead frames () and (), the first and second IC dies () and (), and the at least one stud bump () are encapsulated by a mold compound () to form a 3D package.

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