Intel Corporation

Tahoe Research, Ltd.

Omkar G Karhade

Nitin A Deshpande

Debendra Mallik

Ravindranath Vithal Mahajan

Mitul Bharat Modi

Xiaoqian Li

Shawna M Liff

Edvin Cetegen

Yoshihiro Tomita

Sairam Agraharam

Bassam Mohammed Ziadeh

William J Lambert

Sanka Ganesan

Feras Eid

Robert L Sankman

Eric Jin Li

Robert M Nickerson

Srinivas V Pietambaram

Chia-Pin Chiu

Brandon C Marin

Christopher J Nelson

Zhichao Zhang

Nachiket R Raravikar

Amruthavalli Pallavi Alur

Gang Duan

Manish Dubey

Bai Nie

Sri Chaitra J Chavali

Johanna M Swan

Sasha N Oster

Kemal Aygun

Tim Tri Hoang

John Stephen Guzek

Kyu Oh Lee

Krishna Bharath

Digvijay Ashokkumar Raorane

Rajasekaran Swaminathan

Jeremy D Ecton

Sai Vadlamani

Tarek A Ibrahim

Christopher L Rumer

Yiqun Bai

Charles A Gealer

Jason M Gamba

Aastha Uppal

Abhishek A Sharma

Aleksandar Aleksov

Sujit Sharan

Kristof Darmawikarta

Rahul N Manepalli

Robert Alan May

Islam A Salama

Sri Ranga Sai Boyapati

Wilfred Gomes

Ram S Viswanath

James Chris Matayabas, Jr

Chandra Mohan Jha

Wei-Lun Kane Jen

Rajendra C Dias

Pushkar Ranade

Steve S Cho

Kinya Ichikawa

Bharat P Penmecha

Arnab Sarkar

Tolga Acikalin

Zhenguo Jiang

Guotao Wang

Tahir Ghani

Anand S Murthy

Adel A Elsherbini

Telesphor Kamgaing

Bryan K Casper

James E Jaussi

Wei Ey Li

Yonggang Li

Je-Young Chang

Sidharth Dalmia

Yikang Deng

Ravi V Mahajan

Andrew Paul Collins

Hiroki Tanaka

Suddhasattwa Nad

Sandeep B Sane

Yongki Min

Xavier Francois Brun

Dingying David Xu

Zhimin Wan

Mozhgan Mansuri

Nicholas S Haehn

Jimin Yao

Ankur Agrawal

Gregorio R Murtagian

Amram Eitan

Christopher M Pelto

Weihua Tang

Yosuke Kanaoka

Aravindha Antoniswamy

Sameer Paital

Mohammad Enamul Kabir

Haobo Chen

Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, and a photonics die coupled to the package substrate. In an embodiment, a compute die is coupled to the package substrate, where the photonics die is communicatively coupled to the compute die by a bridge in the package substrate. In an embodiment, the optical package further comprises an optical waveguide embedded in the package substrate. In an embodiment, a first end of the optical waveguide is below the photonics die, and a second end of the optical waveguide is substantially coplanar with an edge of the package substrate.

High bandwidth optical interconnection architectures

Embodiments disclosed herein include semiconductor devices. In one embodiment, a die comprises a substrate, where the substrate comprises a semiconductor material. In an embodiment, a backend layer is over the substrate, where the backend layer comprises conductive routing. In an embodiment, the die further comprises a protrusion extending out from an edge of the substrate and the backend layer. In an embodiment, a fiducial is on a surface of the protrusion.

HBI die architecture with fiducial in street for no metal depopulation in active die

Embodiments of an integrated circuit (IC) die comprise a first region having a first surface and a second surface, the first surface being orthogonal to the second surface; a second region comprising a semiconductor material, the second region attached to the first region along a first planar interface that is orthogonal to the first surface and parallel to the second surface; and a third region comprising optical structures of a photonic IC, the third region attached to the second region along a second planar interface that is parallel to the first planar interface. The first region comprises: a plurality of layers of conductive traces in a dielectric material, each layer of the conductive traces being parallel to the second surface such that the conductive traces are orthogonal to the first surface; and bond-pads on the first surface, the bond-pads comprising portions of respective conductive traces exposed on the first surface.

Package architecture of photonic system with vertically stacked dies having planarized edges

Embodiments of a microelectronic assembly comprise: a plurality of microelectronic sub-assemblies arranged in a coplanar array, each microelectronic sub-assembly having a first side and an opposing second side; a first conductive plate coupled to the first sides of the microelectronic sub-assemblies; and a second conductive plate coupled to the second sides of the microelectronic sub-assemblies. The first conductive plate and the second conductive plate comprise sockets corresponding to each of the microelectronic sub-assemblies, and each microelectronic sub-assembly comprises a first plurality of integrated circuit (IC) dies coupled on one end to a first IC die and on an opposing end to a second IC die; and a second plurality of IC dies coupled to the first IC die and to the second IC die.

Package architecture of scalable compute wall having compute bricks with vertically stacked dies

A reduced bridge structure for a photonic integrated circuit (PIC) or any integrated circuit comprising a ring resonator structure. The reduced bridge structure is an architecture including an optical and electrical routing arrangement to reduce the number of bridges around the micro-ring structure of the ring resonator structure. Embodiments reserve one bridge portion for use as a signal trace, not routing the signal trace over a silicon waveguide. By not routing the signal trace over a silicon waveguide, the structure avoids possible interference between the radio frequency (RF) signal on the signal trace and optical communication (a light wave) propagating in the silicon waveguide.

Reduced bridge structure for a photonic integrated circuit

Techniques and mechanisms for a reconstituted circuit device to be formed using a flow of material, by capillary action, in a region between a first die and a second die. In an embodiment, a rigid mass extends around, and between, the first die and the second die. The rigid mass comprises a first body of a first material, and a second body of second material, wherein the bodies each extend across the region to respective sidewall structures of the first and second dies. In the region, a portion of the first body forms a surface structure which adjoins the second body. A concave or convex shape of the surface structure is an artefact of a meniscus formed by the first material during a liquid state thereof. In another embodiment, the reconstituted circuit device further comprises an interconnect which adjoins, and extends through, the rigid mass.

Formation of a reconstituted circuit device using flow of a material by capillary action

Embodiments disclosed herein include optical systems with Faraday rotators in order to enhance efficiency. In an embodiment, a photonics package comprises an interposer and a patch over the interposer. In an embodiment, the patch overhangs an edge of the interposer. In an embodiment, the photonics package further comprises a photonics die on the patch and a Faraday rotator passing through a thickness of the patch. In an embodiment, the Faraday rotator is below the photonics die.

Faraday rotator interconnect as a through-via configuration in a patch architecture

Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra-fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die-to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

Ultra-thin, hyper-density semiconductor packages

Stacked die assemblies having a moisture sealant layer according to embodiments are described herein. A microelectronic package structure having a first die with a second and an adjacent third die on the first die. Each of the second and third die comprise hybrid bonding interfaces with the first die. A first layer is on a region of the first die adjacent sidewalls of the second and the third dies, and adjacent an edge portion of the first die. The first layer comprises a diffusion barrier material A second layer is over the first layer, the second layer, wherein a top surface of the second layer is substantially coplanar with the top surfaces of the second and third dies. The first layer provides a hermetic moisture sealant layer for stacked die package structures.

Moisture seal coating of hybrid bonded stacked die package assembly

Embodiments disclosed herein include an on-cavity photonic integrated circuit (OCPIC). In an embodiment, the OCPIC comprises a laser transmitter, that comprises a row with four bumps, and a micro-ring resonator (MRR) in the row between a first bump and a second bump of the four bumps. In an embodiment, a cavity is below the MRR, where a diameter of the cavity is substantially equal to a spacing between the first bump and the second bump.

On-cavity photonic integrated circuit (OCPIC) to achieve the most undercut real estate for effective thermal tuning

Embodiments disclosed herein include an optoelectronic system. In an embodiment, the optoelectronic system comprises a first substrate, a second substrate over the first substrate, and a micro-ring resonator (MRR) over the second substrate. In an embodiment, a heater is integrated into the MRR, a cladding is over the MRR, and a temperature sensor is over the MRR in the cladding.

Temperature sensor to achieve thermal stabilization of micro-ring resonator (MRR) in an open cavity photonic integrated circuit (OCPIC)

Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

Microelectronic structures including bridges

Embodiments disclosed herein include optoelectronic systems and methods of forming such systems. In an embodiment, an optoelectronic system comprises a first substrate, a second substrate over the first substrate, a micro-ring resonator (MRR) over the second substrate, a heater integrated into the MRR, a cladding over the MRR, an opening through the first substrate and the second substrate to expose a bottom surface of the MRR, and a base spanning across the opening.

Undercut design with a bonded base cover for friendly assembly and effective thermal tuning of micro-ring resonator (MRR) in open cavity photonic integrated chips (OCPIC)

An optoelectronic assembly is disclosed, comprising a substrate having a core comprised of glass, and a photonic integrated circuit (PIC) and an electronic IC (EIC) coupled to a first side of the substrate. The core comprises a waveguide with a first endpoint proximate to the first side and a second endpoint exposed on a second side of the substrate orthogonal to the first side. The first endpoint of the waveguide is on a third side of the core parallel to the first side of the substrate. The substrate further comprises an optical via aligned with the first endpoint, and the optical via extends between the first side and the third side. In various embodiments, the waveguide is of any shape that can be inscribed by a laser between the first endpoint and the second endpoint.

Nested glass packaging architecture for hybrid electrical and optical communication devices

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL includes conductive vias having a greater width towards a first surface of the RDL and a smaller width towards an opposing second surface of the RDL; wherein the first surface of the RDL is electrically coupled to the second surface of the first die by first solder interconnects having a first solder; and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by second solder interconnects having a second solder, wherein the second solder is different than the first solder.

Microelectronic assemblies including interconnects with different solder materials

Growing community of inventors

Chandler, AZ, United States of America

Omkar G Karhade