Intel Corporation

Tahoe Research, Ltd.

Omkar G Karhade

Nitin A Deshpande

Debendra Mallik

Shawna M Liff

Mitul Bharat Modi

Ravindranath Vithal Mahajan

Edvin Cetegen

Xiaoqian Li

Yoshihiro Tomita

Sairam Agraharam

Bassam Mohammed Ziadeh

Sanka Ganesan

William J Lambert

Mohit Bhatia

Feras Eid

Robert L Sankman

Eric Jin Li

Robert M Nickerson

Christopher J Nelson

Chia-Pin Chiu

Nachiket R Raravikar

Manish Dubey

Sri Chaitra J Chavali

Kedar Dhane

Johanna M Swan

Srinivas V Pietambaram

Sasha N Oster

Tim Tri Hoang

Kemal Aygun

John Stephen Guzek

Zhichao Zhang

Kyu Oh Lee

Brandon C Marin

Krishna Bharath

Digvijay Ashokkumar Raorane

Rajasekaran Swaminathan

Amruthavalli Pallavi Alur

Gang Duan

Tarek A Ibrahim

Christopher L Rumer

Yiqun Bai

Charles A Gealer

Bai Nie

Aastha Uppal

Kaveh Hosseini

Aleksandar Aleksov

Islam A Salama

James Chris Matayabas, Jr

Ram S Viswanath

Jeremy D Ecton

Chandra Mohan Jha

Wei-Lun Kane Jen

Rajendra C Dias

Steve S Cho

Kinya Ichikawa

Bharat P Penmecha

Jason M Gamba

Guotao Wang

Zhenguo Jiang

Tolga Acikalin

Tyler N Osborn

Jiro Kubota

Lars D Skoglund

Aditya Sundoctor Vaidya

Zhaozhi Li

Adel A Elsherbini

Sujit Sharan

Telesphor Kamgaing

Kristof Darmawikarta

Rahul N Manepalli

Robert Alan May

Wei Ey Li

Sri Ranga Sai Boyapati

Yonggang Li

Je-Young Chang

Sidharth Dalmia

Yikang Deng

Ravi V Mahajan

Sai Vadlamani

Andrew Paul Collins

Suddhasattwa Nad

Sandeep B Sane

Yongki Min

Xavier Francois Brun

Dingying David Xu

Zhimin Wan

Nicholas S Haehn

Jimin Yao

Gregorio R Murtagian

Amram Eitan

Christopher M Pelto

Weihua Tang

Yosuke Kanaoka

Aravindha Antoniswamy

Mohammad Enamul Kabir

Arnab Sarkar

Thomas J De Bonis

Haobo Chen

Ziyin Lin

Timothy A Gosselin

Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra-fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die-to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

Ultra-thin, hyper-density semiconductor packages

Stacked die assemblies having a moisture sealant layer according to embodiments are described herein. A microelectronic package structure having a first die with a second and an adjacent third die on the first die. Each of the second and third die comprise hybrid bonding interfaces with the first die. A first layer is on a region of the first die adjacent sidewalls of the second and the third dies, and adjacent an edge portion of the first die. The first layer comprises a diffusion barrier material A second layer is over the first layer, the second layer, wherein a top surface of the second layer is substantially coplanar with the top surfaces of the second and third dies. The first layer provides a hermetic moisture sealant layer for stacked die package structures.

Moisture seal coating of hybrid bonded stacked die package assembly

Embodiments disclosed herein include an on-cavity photonic integrated circuit (OCPIC). In an embodiment, the OCPIC comprises a laser transmitter, that comprises a row with four bumps, and a micro-ring resonator (MRR) in the row between a first bump and a second bump of the four bumps. In an embodiment, a cavity is below the MRR, where a diameter of the cavity is substantially equal to a spacing between the first bump and the second bump.

On-cavity photonic integrated circuit (OCPIC) to achieve the most undercut real estate for effective thermal tuning

Embodiments disclosed herein include an optoelectronic system. In an embodiment, the optoelectronic system comprises a first substrate, a second substrate over the first substrate, and a micro-ring resonator (MRR) over the second substrate. In an embodiment, a heater is integrated into the MRR, a cladding is over the MRR, and a temperature sensor is over the MRR in the cladding.

Temperature sensor to achieve thermal stabilization of micro-ring resonator (MRR) in an open cavity photonic integrated circuit (OCPIC)

Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

Microelectronic structures including bridges

Embodiments disclosed herein include optoelectronic systems and methods of forming such systems. In an embodiment, an optoelectronic system comprises a first substrate, a second substrate over the first substrate, a micro-ring resonator (MRR) over the second substrate, a heater integrated into the MRR, a cladding over the MRR, an opening through the first substrate and the second substrate to expose a bottom surface of the MRR, and a base spanning across the opening.

Undercut design with a bonded base cover for friendly assembly and effective thermal tuning of micro-ring resonator (MRR) in open cavity photonic integrated chips (OCPIC)

An optoelectronic assembly is disclosed, comprising a substrate having a core comprised of glass, and a photonic integrated circuit (PIC) and an electronic IC (EIC) coupled to a first side of the substrate. The core comprises a waveguide with a first endpoint proximate to the first side and a second endpoint exposed on a second side of the substrate orthogonal to the first side. The first endpoint of the waveguide is on a third side of the core parallel to the first side of the substrate. The substrate further comprises an optical via aligned with the first endpoint, and the optical via extends between the first side and the third side. In various embodiments, the waveguide is of any shape that can be inscribed by a laser between the first endpoint and the second endpoint.

Nested glass packaging architecture for hybrid electrical and optical communication devices

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL includes conductive vias having a greater width towards a first surface of the RDL and a smaller width towards an opposing second surface of the RDL; wherein the first surface of the RDL is electrically coupled to the second surface of the first die by first solder interconnects having a first solder; and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by second solder interconnects having a second solder, wherein the second solder is different than the first solder.

Microelectronic assemblies including interconnects with different solder materials

Disclosed herein are microelectronic structures including bridges, and related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate with first and second metal layers; a cavity in the substrate, where a portion of the first and second metal layers, are exposed with the portion of the first metal layer partially overlapping the portion of the second metal layer; and a bridge component in the cavity, having a first conductive contact at a first face and a second conductive contact at a second face opposing the first face, the second face towards a bottom surface of the cavity, the portion of the first metal layer is between the second face of the bridge component and the portion of the second metal layer, and the second conductive contact is electrically coupled to the portion of the second metal layer in the cavity.

Integrated circuit assemblies can be fabricated on a wafer scale, wherein a base template, having a plurality of openings, may cover a base substrate, such as a die wafer, wherein the base substrate has a plurality of first integrated circuit devices formed therein and wherein at least one second integrated circuit device is electrically attached to a corresponding first integrated circuit device through a respective opening in the base template. Thus, when the base substrate and base template are singulated into individual integrated circuit assemblies, the individual integrated circuit assemblies will each have a first integrated circuit that is edge aligned to a singulated portion of the base template. The singulated portion of the base template can provide an improved thermal path, mechanical strength, and/or electrical paths for the individual integrated circuit assemblies.

Edge-aligned template structure for integrated circuit packages

Microelectronic assemblies including photonic integrated circuits (PICs), related devices and methods, are disclosed herein. For example, in some embodiments, a photonic assembly may include a PIC in a first layer including an insulating material, wherein the PIC has an active side and an opposing backside, and wherein the PIC is embedded in the insulating material with the active side facing down; a conductive pillar in the first layer; an integrated circuit (IC) in a second layer, wherein the second layer is on the first layer, wherein the second layer includes the insulating material and the IC is embedded in the insulating material in the second layer, and wherein the IC is electrically coupled to the backside of the PIC and the conductive pillar; and an optical component optically coupled to the active surface of the PIC.

Photonic integrated circuit packaging architectures

Microelectronic assemblies including photonic integrated circuits (PICs), related devices and methods, are disclosed herein. For example, in some embodiments, a photonic assembly may include a PIC in a first layer including an insulating material, wherein the PIC is embedded in the insulating material with an active surface facing up; a conductive pillar in the first layer; an integrated circuit (IC) in a second layer on the first layer, wherein the second layer includes the insulating material and the IC is embedded in the insulating material, and wherein the IC is electrically coupled to the active surface of the PIC and the conductive pillar; an optical component optically coupled to the active surface of the PIC; and a hollow channel surrounding the optical component, the hollow channel extending from the active surface of the PIC through the insulating material in the second layer.

Embodiments described herein may be related to apparatuses, processes, and techniques for coupling a micro-lens array to a photonics die. In embodiments, this coupling may be performed as an attach at a wafer level. In embodiments, wafer level optical testing of the photonics die with the attached micro-lens array may be tested electrically and optically before the photonics die is assembled into a package, in various configurations. Other embodiments may be described and/or claimed.

Micro-lens array optically coupled with a photonics die

An electronic assembly, such as an integrated circuit package, may be formed comprising a package substrate and a photonic integrated circuit device attached thereto, wherein the package substrate includes a heat dissipation structure disposed therein. A back surface of the photonic integrated circuit device may thermally coupled to the heat dissipation structure within the package substrate for the removal of heat from the photonic integrated circuit device, which allows for access to an active surface of the photonic integrated circuit device for the attachment of fiber optic cables and eliminates the need for a heat dissipation device to be thermally attached to the active surface of the photonic integrated circuit device.

Heat dissipation structures for optical communication devices

Growing community of inventors

Chandler, AZ, United States of America

Omkar G Karhade