International Business Machines Corporation

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Samsung Electronics Co., Ltd.

Omer H Dokumaci

Dureseti Chidambarrao

Bruce Bennett Doris

Oleg Gluschenkov

Huilong Zhu

Jack Allan Mandelman

Carl John Radens

Suryanarayan G Hegde

Meikei Ieong

Huajie Chen

Edward J Nowak

Lawrence Alfred Clevenger

Andres Bryant

Hussein Ibrahim Hanafi

Michael P Belyansky

Kaushik Arun Kumar

Thomas Safron Kanarsky

Erin C Jones

Cyril Cabral, Jr

Werner A Rausch

Kathryn Wilder Guarini

Rajesh Rengarajan

Jeffrey W Sleight

Ying Di Zhang

Shreesh Narasimha

Marwan H Khater

Rajarao Jammy

Rajendran Krishnasamy

Kathryn Turner Schonenberg

Gregory Gower Freeman

Hiroyuki Akatsu

Yujun Li

Paul Andrew Ronsheim

Victor Ku

Richard D Kaplan

Mukesh Vijay Khare

John Michael Hergenrother

Xavier Baie

Brent A Anderson

David V Horak

Josephine B Chang

Alper Buyuktosunoglu

Christian Lavoie

Xinlin Wang

Robert J Purtell

An L Steegen

Atul Champaklal Ajmera

Fen Fen Jamin

Woo-Hyeong Lee

Peter I Smeys

Isabel Ying Yang

Michael Belyanksy

Jack Allen Mandelman

Duresti Chidambarrao

Suryanararyan G Hegde

Oleg Gluschenkev

Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a stressing layer on a substrate. The method may include doping the stressing layer with dopants. The method may include forming a silicide layer on the stressing layer. Moreover, the stressing layer may include a first lattice constant different from a second lattice constant of the substrate.

High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture

A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process to form a first island and second island at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island and the second island. The STI relaxes and facilitates the relaxation of the first island and the second island. The first material may be deposited or grown Ge material and the second material may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island and the second island.

Silicon device on SI:C-OI and SGOI and method of manufacture

A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown in source and drain regions of the nFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel.

Silicon device on Si: C-oi and Sgoi and method of manufacture

Silicon device on Si:C-OI and SGOI and method of manufacture

High performance stress-enhanced MOSFETS using Si:C and SiGe epitaxial source/drain and method of manufacture

Silicon device on Si:C SOI and SiGe and method of manufacture

A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.

Ultra shallow junction formation by epitaxial interface limited diffusion

The present invention provides a semiconducting device including a gate region positioned on a mesa portion of a substrate; and a nitride liner positioned on the gate region and recessed surfaces of the substrate adjacent to the gate region, the nitride liner providing a stress to a device channel underlying the gate region. The stress produced on the device channel is a longitudinal stress on the order of about 275 MPa to about 450 MPa.

Embedded stressed nitride liners for CMOS performance improvement

A method patterns pairs of semiconducting fins on an insulator layer and then patterns a linear gate conductor structure over and perpendicular to the fins. Next, the method patterns a mask on the insulator layer adjacent the fins such that sidewalls of the mask are parallel to the fins and are spaced from the fins a predetermined distance. The method performs an angled impurity implant into regions of the fins not protected by the gate conductor structure and the mask. This process forms impurity concentrations within the fins that are asymmetric and that mirror one another in adjacent pairs of fins.

FinFETs single-sided implant formation

A method for forming a semiconductor substrate structure is provided. A compressively strained SiGe layer is formed on a silicon substrate. Atoms are ion-implanted onto the SiGe layer to cause end-of-range damage. Annealing is performed to relax the strained SiGe layer. During the annealing, interstitial dislocation loops are formed as uniformly distributed in the SiGe layer. The interstitial dislocation loops provide a basis for nucleation of misfit dislocations between the SiGe layer and the silicon substrate. Since the interstitial dislocation loops are distributed uniformly, the misfit locations are also distributed uniformly, thereby relaxing the SiGe layer. A tensilely strained silicon layer is formed on the relaxed SiGe layer.

Strained silicon on relaxed sige film with uniform misfit dislocation density

A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer; a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.

Self-aligned planar double-gate transistor structure

An apparatus and method for controlling the net doping in the active region of a semiconductor device in accordance with a gate length is provided. A compensating dopant is chosen to be a type of dopant which will electrically neutralize dopant of the opposite type in the substrate. By implanting the compensating dopant at relatively high angle and high energy, the compensating dopant will pass into and through the gate region for short channels and have little or no impact on the total dopant concentration within the gate region. Where the channel is of a longer length, the high implant angle and the high implant energy cause the compensating dopant to lodge within the channel thereby neutralizing a portion of the dopant of the opposite type.

Anti-halo compensation

Superior control of short-channel effects for an ultra-thin semiconductor-on-insulator field effect transistor (UTSOI-FET) is obtained by performing a halo implantation immediately after a gate reoxidation step. An offset is then formed and thereafter an extension implantation process is performed. This sequence of processing steps ensures that the halo implant is laterally separated from the extension implant by the width of the offset spacer. This construction produces equivalent or far superior short channel performance compared to conventional UTSOI-FETs. Additionally, the above processing steps permit the use of lower halo doses as compared to conventional processes.

Halo-first ultra-thin SOI FET for superior short channel control

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Wappingers Falls, NY, United States of America

Omer H Dokumaci