Freescale Semiconductor,inc.

Motorola Corporation

Motorlola, Inc.

Olubunmi O Adetutu

Dina H Triyoso

Philip J Tobin

Hsing H Tseng

Ted R White

Bich-Yen Nguyen

Tien Ying Luo

Marius K Orlowski

James Kenyon Schaeffer, Iii

Yeong-Jyh Tom Lii

David Gilmer

Mariam G Sadaka

Chitra K Subramanian

James D Hayden

Robert E Jones

Paul Grudowski

Bikas Maiti

Kevin D Lucas

Christopher C Hobbs

Yolanda S Musgrove

Voon-Yew Thean

Srikanth Balaji Samavedam

William James Taylor, Jr

Alexander Barr

Dean J Denning

Arkalgud R Sitaram

Eric D Luckowski

Narayanan C Ramani

Randy W Cotton

Darrell Roan

Rajeev Bajaj

Shahid Rauf

Mark Douglas Hall

Wei E Wu

Suresh Venkatesan

Douglas Michael Reber

Craig T Swift

Tab Allen Stephens

Peter L G Ventzek

Rama I Hegde

Bruce E White

Hsing-Huang Tseng

Dharmesh Jawarani

Paul A Ingersoll

Matthew Thomas Herrick

Alexander L Barr

Cindy Reidsema Simpson

John M Grant

Kathleen C Yu

Ajay Jain

Sriram Kalpat

Marc A Rossow

Stuart E Greer

Sangwoo Lim

Ramnath Venkatraman

Subramoney V Iyer

Vidya S Kaushik

Rajan Nagabushnam

Brian George Anthony

David Clegg

Sanjit K Das

Lynne M Michaelson

Mark G Fernandes

Arturo Manuel Martinez, Jr

Steven G H Anderson

Tien-Ying Luo

James K Schaeffer, Iii

Mark C Foisy

Anna M Phillips

Gregor Braeckelmann

Rina Chowdhury

Stephen R Crown

Rebecca G Cole

Archana Redkar

Anthony Mark Miscione

J Olufemi Olowolafe

Phillip J Stout

Robert E Jones Jr

Jeffrey W Thomas

Christopher B Hundley

Donald O Arugu

A transistor structure of an electronic device can include a gate dielectric layer and a gate electrode. The gate electrode can have a surface portion between the gate dielectric layer and the rest of the gate electrode. The surface portion can be formed such that another portion of the gate electrode primarily sets the effective work function in the finished transistor structure.

Electronic device with a gate electrode having at least two portions

A method and apparatus are described for forming a first inter-layer dielectric (ILD0) stack having a protective gettering layer () with a substantially uniform thickness. After forming device components () on a substrate (), a gap fill dielectric layer of SATEOS () is deposited over an etch stop layer of PEN ESL () and then planarized before sequentially depositing a gettering layer of BPTEOS () and capping dielectric layer () on the planarized gap fill dielectric layer (). Once the ILD0 stack is formed, one or more contact openings () are etched through the ILD0 stack, thereby exposing the etch stop layer () over the intended contact regions.

First inter-layer dielectric stack for non-volatile memory

A method for forming a shared contact in a semiconductor device having a gate electrode corresponding to a first transistor and a source/drain region corresponding to a second transistor is provided. The method includes forming a first opening in a dielectric layer overlying the gate electrode and the source/drain region, wherein the first opening extends substantially to the gate electrode corresponding to the first transistor. The method further includes after forming the first opening, forming a second opening, contiguous with the first opening, in the overlying dielectric layer, wherein the second opening extends substantially to the source/drain region corresponding to the second transistor. The method further includes forming the shared contact between the gate electrode corresponding to the first transistor and the source/drain region corresponding to the second transistor by filling the first opening and the second opening with a conductive material.

Method of forming a shared contact in a semiconductor device

A semiconductor process and apparatus includes forming first and second gate electrodes () by forming the first gate electrode () over a first high-k gate dielectric () and forming the second gate electrode () over at least a second high-k gate dielectric () different from the first gate dielectric (). Either or both of the high-k gate dielectric layers () may be formed by depositing and selectively etching an initial layer of high-k dielectric material (e.g.,). As deposited, the initial layer () has an exposed surface () and an initial predetermined crystalline structure. An exposed thin surface layer () of the initial layer () is prepared for etching by modifying the initial crystalline structure in the exposed thin surface layer. The modified crystalline structure in the exposed thin surface layer may be removed by applying a selective etch, such as HF or HCl.

Reverse ALD

A semiconductor process and apparatus includes forming first and second metal gate electrodes () over a hybrid substrate () by forming the first gate electrode () over a first high-k gate dielectric () and forming the second gate electrode () over at least a second high-k gate dielectric () different from the first gate dielectric (). By forming the first gate electrode () over a first SOI substrate () formed by depositing (100) silicon and forming the second gate electrode () over an epitaxially grown (110) SiGe substrate (), a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes () having improved hole mobility.

Modified hybrid orientation technology

A method for forming a dielectric layer is provided. The method may include providing a semiconductor surface and etching a thin layer of the semiconductor substrate to expose a surface of the semiconductor surface, wherein the exposed surface is hydrophobic. The method may further include treating the exposed surface of the semiconductor substrate with plasma to neutralize a hydrophobicity associated with the exposed surface, wherein the exposed surface is treated using plasma with a power in a range of 100 watts to 500 watts and for duration in a range of 1 to 60 seconds. The method may further include forming a metal-containing layer on a top surface of the plasma treated surface using an atomic layer deposition process.

Plasma treatment of a semiconductor surface for enhanced nucleation of a metal-containing layer

A method of forming a gate dielectric layer includes forming a first dielectric layer over a semiconductor substrate using a first plasma, performing a first in-situ plasma nitridation of the first dielectric layer to form a first nitrided dielectric layer, forming a second dielectric layer over the first dielectric layer using a second plasma, performing a second in-situ plasma nitridation of the second dielectric layer to form a second nitrided dielectric layer; and annealing the first nitrided dielectric layer and the second nitrided dielectric layer, wherein the gate dielectric layer comprises the first nitrided dielectric layer and the second nitrided dielectric layer. In other embodiments, the steps of forming a dielectric layer using a plasma and performing an in-situ plasma nitridation are repeated so that more than two nitrided dielectric layers are formed and used as the gate dielectric layer.

Method of forming a gate dielectric by in-situ plasma

One or more impurities may be incorporated within a metal-containing layer of a metal-containing gate electrode to modify the work function of the metal-containing gate electrode of a transistor can affect the threshold voltage of the transistor. In one embodiment, the impurity can be used in a p-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the valence band for silicon. In another embodiment, the impurity can be used in an n-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the conduction band for silicon. In a particular embodiment, a boron-containing species is implanted into a metal-containing layer within the metal-containing gate electrode within a p-channel transistor, so that the metal-containing gate electrode has a work function closer to the valence band for silicon as compared to the metal-containing gate electrode without the boron-containing species.

Electronic device comprising a gate electrode including a metal-containing layer having one or more impurities

A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch a gate stack () formed over a substrate (), thereby forming an etched gate () having a vertical sidewall profile (). By constructing the gate stack () with a graded material composition of silicon-based layers, the composition of which is selected to counteract the etching tendencies of the predetermined sequence of patterning and etching steps, a more idealized vertical gate sidewall profile () may be obtained.

Method to control the gate sidewall profile by graded material composition

A method for forming a via includes forming a gate electrode over a semiconductor substrate, forming a source/drain region in the semiconductor substrate adjacent the gate electrode, forming a silicide region in the source/drain region, forming a post-silicide spacer adjacent the gate electrode after forming the silicide region, forming an interlayer dielectric layer over the gate electrode, the post-silicide spacer, and the silicide region, and forming a conductive via in the interlayer dielectric layer, extending to the silicide region.

Method of forming a via

A semiconductor fabrication process for forming a gate dielectric includes depositing a high-k dielectric stack including incorporating nitrogen into the high-k dielectric stack in-situ. A top high-k dielectric is formed overlying the dielectric stack and the dielectric stack and the top dielectric are annealed. Depositing the dielectric stack includes depositing a plurality of high-k dielectric layers where each layer is formed in a distinct processing step or set of steps. Depositing one of the dielectric layers includes performing a plurality of atomic layer deposition processes to form a plurality of high-k sublayers, wherein each sublayer is a monolayer film. Depositing the plurality of sublayers includes depositing a nitrogen free sublayer and depositing a nitrogen bearing sublayer. Depositing the nitrogen free sublayer includes pulsing an ALD chamber with HfCl, purging the chamber with an inert, pulsing the chamber with an HO or DO, and purging the chamber with an inert.

In-situ nitridation of high-k dielectrics

Process of forming an electronic device including active regions and gate electrodes of different compositions overlying the active regions

A metal layer etch process deposits, patterns and anisotropically etches a polysilicon layer () down to an underlying metal layer () to form an etched polysilicon structure () with polymer layers () formed on its sidewall surfaces. The polymer layer () are removed to expose an additional surface area () of the metal layer (), and dielectric layers () are formed on the sidewall surfaces of the etched polysilicon structure (). Next, the metal layer () is plasma etched to form an etched metal layer () with substantially vertical sidewall surfaces () by simultaneously charging the dielectric layers () to change plasma ion trajectories near the dielectric layers () so that plasma ions () impact the sidewall surfaces () in a more perpendicular angle to enhance etching of the sidewall surfaces () of the etched metal layer ().

Method for removing metal foot during high-k dielectric/metal gate etching

A semiconductor process and apparatus provide a polysilicon structure () and source/drain regions () formed adjacent thereto in which a dual silicide scheme is used to form first silicide regions in the polysilicon, source and drain regions () using a first metal (e.g., cobalt). After forming sidewall spacers (), a second metal (e.g., nickel) is used to form second silicide regions in the polysilicon, source and drain regions () to reduce encroachment by the second silicide in the source/drain () and to reduce resistance in the polysilicon structure caused by agglomeration and voiding from the first silicide ().

Dual metal silicide scheme using a dual spacer process

Growing community of inventors

Austin, TX, United States of America

Olubunmi O Adetutu