Advanced Micro Devices Corporation

Intermolecular, Inc.

Globalfoundries Inc.

Spansion Llc.

Olov B Karlsson

Christopher F Lyons

Effiong Etukudo Ibok

Larry Lingjer Wang

Nick Kepler

Basab Bandyopadhyay

Anh Duong

Minh Van Ngo

Scott Allan Bell

William George En

Bin Yu

Usha Raghuram

Qi Xiang

Haihong Wang

John S Foster

Clemens Fitz

Zhendong Hong

Zoran Krivokapic

David Keating Foote

Amol Ramesh Joshi

Ashish Bodke

Bei Li

James Mavrinac

Paul Raymond Besser

Divya Pisharoty

Hoon Sik Kim

Kisik Choi

Jinping Liu

Chih-Yuh Yang

Sean Barstow

Maria Chow Chan

Salil Mujumdar

Susie Tzeng

Bin Yang

Dipankar Pramanik

Mark W Michael

Simon S Chan

Timothy J Thurgate

Suketu Arun Parikh

Robert B Ogle

Dong-Hyuk Ju

Shankar Sinha

Mark V Raymond

Wei Long

Kevin Kashefi

Ratsamee Limdulpaiboon

Bongki Lee

Nobi Fuchigami

Charlene Chen

Jingang Su

Bill Yowjuang Liu

Sven Metzger

Daniel A Steckert

Yun Sun

Chih-Yuk Yang

Basab Bandyopadhyah

Effiong Obok

Basab Bandyophadhyay

A method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process is disclosed, including a multi-step residue cleaning, including exposing the substrate to an aqua regia solution, followed by an exposure to a solution having hydrochloric acid and hydrogen peroxide. The SC2 solution can further react with remaining platinum residues, rendering it more soluble in an aqueous solution and thereby dissolving it from the surface of the substrate.

Aqua regia and hydrogen peroxide HCL combination to remove Ni and NiPt residues

An integrated circuit product includes an NMOS transistor having a gate structure that includes an NMOS gate insulation layer, a first NMOS metal layer positioned on the NMOS gate insulation layer, an NMOS metal silicide material positioned above the first NMOS metal layer, and a layer of a second metal material positioned above and in contact with the NMOS gate insulation layer, the first NMOS metal layer, and the NMOS metal silicide layer. The PMOS transistor has a gate structure that includes a PMOS gate insulation layer, a first PMOS metal layer positioned on the PMOS gate insulation layer, a PMOS metal silicide material positioned above the first PMOS metal layer, and a layer of the second metal material positioned above and in contact with the PMOS gate insulation layer, the first PMOS metal layer, and the PMOS metal silicide layer.

Gate structures for transistor devices for CMOS applications and products

Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an interlayer of dielectric oxide material in a FET region and overlying a semiconductor substrate. A high-K dielectric layer is deposited overlying the interlayer. Fluorine is incorporated into the interlayer and/or the high-K dielectric layer.

Methods for fabricating integrated circuits including fluorine incorporation

One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities.

Methods of forming gate structures for transistor devices for CMOS applications

Methods to form metal gate transistor devices are disclosed. Erbium silicide layers can be used in CMOS transistors in which the work function of the erbium silicide layers can be tuned for use in PMOS and NMOS devices. A nanolaminate sputtering approach can be used in which silicon and erbium layers are alternatingly deposited to determine optimum layer properties, composition profiles, and erbium to silicon ratios for a particular gate stack.

Method of forming an erbium silicide metal gate stack FinFET device via a physical vapor deposition nanolaminate approach

Aqua regia and hydrogen peroxide HCI combination to remove Ni and NiPt residues

The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process. Post silicidation residues of nickel and platinum may not be removed adequately just by an aqua regia solution (comprising a mixture of nitric acid and hydrochloric acid). Therefore, embodiments of the invention provide a multi-step residue cleaning, comprising exposing the substrate to an aqua regia solution, followed by an exposure to a chlorine gas or a solution comprising dissolved chlorine gas, which may further react with remaining platinum residues, rendering it more soluble in aqueous solution and thereby dissolving it from the surface of the substrate.

Process to remove Ni and Pt residues for NiPtSi application using chlorine gas

Methods and structures are described for determining contact resistivities and Schottky barrier heights for conductors deposited on semiconductor wafers that can be combined with combinatorial processing, allowing thereby numerous processing conditions and materials to be tested concurrently. Methods for using multi-ring as well as single-ring CTLM structures to cancel parasitic resistance are also described, as well as structures and processes for inline monitoring of properties.

Circular transmission line methods compatible with combinatorial processing of semiconductors

Provided are methods for processing semiconductor substrates to remove high-dose ion implanted (HDI) photoresist structures without damaging other structures made of titanium nitride, tantalum nitride, hafnium oxide, and/or hafnium silicon oxide. The removal is performed using a mixture of an organic solvent, an oxidant, a metal-based catalyst, and one of a base or an acid. Some examples of suitable organic solvents include dimethyl sulfoxide, n-ethyl pyrrolidone, monomethyl ether, and ethyl lactate. Transition metals in their zero-oxidation state, such as metallic iron or metallic chromium, may be used as catalysts in this mixture. In some embodiments, a mixture includes ethyl lactate, of tetra-methyl ammonium hydroxide, and less than 1% by weight of the metal-based catalyst. The etching rate of the HDI photoresist may be at least about 100 Angstroms per minute, while other structures may remain substantially intact.

High dose ion-implanted photoresist removal using organic solvent and transition metal mixtures

Aqua regia and hydrogen peroxide HCl combination to remove Ni and NiPt residues

A method for cleaning platinum residues from a surface of a substrate is provided. The method initiates with exposing the surface to a first solution containing a mixture of nitric acid and hydrochloric acid. Then, the surface is exposed to a second solution containing hydrochloric acid.

Method for cleaning platinum residues on a semiconductor substrate

Metal gate high-k capacitor structures with lithography patterning are used to extract gate work function using a combinatorial workflow. Oxide terracing, together with high productivity combinatorial process flow for metal deposition can provide optimum high-k gate dielectric and metal gate solutions for high performance logic transistors. The high productivity combinatorial technique can provide an evaluation of effective work function for given high-k dielectric metal gate stacks for PMOS and NMOS transistors, which is critical in identifying and selecting the right materials.

High productivity combinatorial oxide terracing and PVD/ALD metal deposition combined with lithography for gate work function extraction

The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process, comprising using an aqua regia cleaning solution (comprising a mixture of nitric acid and hydrochloric acid) with microwave assisted heating. Low boiling temperature of hydrochloric acid prevents heating the aqua regia solution to a high temperature, impeding the effectiveness of post silicidation nickel and platinum residue removal. Therefore, embodiments of the invention provide a microwave assisted heating of the substrate in an aqua regia solution, selectively heating platinum residues without significantly increasing the temperature of the aqua regia solution, rendering platinum residues to be more soluble in aqueous solution and thereby dissolving it from the surface of the substrate.

Process to remove Ni and Pt residues for NiPtSi applications using aqua regia with microwave assisted heating

The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process. Embodiments of the invention provide a multi-step cleaning process, comprising exposing the substrate to a nitric acid solution after a first anneal, followed by an aqua regia solution after a second anneal. The substrate can be optionally exposed to a hydrochloric acid solution afterward to completely remove any remaining platinum residues.

Process to remove Ni and Pt residues for NiPtSi applications

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San Jose, CA, United States of America

Olov B Karlsson