Applied Materials, Inc.

Centre National De La Recherche Scientifique

Commissariat a L'energie Atomique Et Aux Energies Alternatives

Other

France Telecom

Université Joseph Fourier

Electricite De France

Université Grenoble Alpes

Commissariat À L'énergie Atomique Et Aux Énergies Alternatives

Centre National De La Recherche Scientifique-cnrs

Université Joseph Fourier - Grenoble

Olivier Joubert

Nicolas Posseme

Olivier Luere

Rajinder Dhindsa

Philip Allan Kraus

James Rogers

Laurent J Vallier

Leonid Dorf

Travis Koh

Vedapuram S Achutharaman

Maxime Darnon

Yves Piffard

Maria Teresa Caldes-Rouillon

Srinivas D Nemani

Dmitry Lubomirsky

Thorsten B Lill

Timothy Weidman

David S Mui

Leonard Michael Tedeschi

Sunil Srinivasan

Dian Sugiarto

Jason Andrew Kenney

Daniel Thomas McCormick

Eric Puzenat

Luc Brohan

Lili Ji

Thibaut David

Hari Sutrisno

Annabelle Rouet

David Fuard

Cedric Monget

Ying Di Zhang

Bernard Dieny

Samer Banna

Lei Lian

Benjamin Schwarz

Tom K Choi

Qingjun Zhou

Philippe Stevens

Gabriele Navarro

Sebastien Barnola

YungChen Lin

Gilles Cunge

Emilie Despiau-Pujo

Jérémy Gilbert Maurice Pereira

Kevin Menguelti

Erwine Maude Pargon

Johann Foucher

Giles Cunge

Marceline Bonvalot

Sophie Vallon

Aurelien Tavernier

C&eacute;dric Monget

Thibaud Delahaye

Erwine Pargon

Torsten Lill

Systems and methods for creating arbitrarily-shaped ion energy distribution functions using shaped-pulse-bias. In an embodiment, a method includes applying a positive jump voltage to an electrode of a process chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and modulating the amplitude of the wafer voltage to produce a predetermined number of pulses to determine an ion energy distribution function. In another embodiment a method includes applying a positive jump voltage to an electrode of a process chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and applying a ramp voltage to the electrode that overcompensates for ion current on the wafer or applying a ramp voltage to the electrode that undercompensates for ion current on the wafer.

Creating ion energy distribution functions (IEDF)

Systems and methods for creating arbitrarily-shaped ion energy distribution functions using shaped-pulse&#x2014;bias. In an embodiment, a method includes applying a positive jump voltage to an electrode of a process chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and modulating the amplitude of the wafer voltage to produce a predetermined number of pulses to determine an ion energy distribution function. In another embodiment a method includes applying a positive jump voltage to an electrode of a process chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and applying a ramp voltage to the electrode that overcompensates for ion current on the wafer or applying a ramp voltage to the electrode that undercompensates for ion current on the wafer.

The implementations described herein generally relate to a process kit suitable for use in a semiconductor process chamber, which reduces edge effects and widens the processing window with a single edge ring as compared to conventional process kits. The process kit generally includes an edge ring disposed adjacent to and surrounding a perimeter of a semiconductor substrate in a plasma chamber. A dimension of a gap between the substrate and the edge ring is less than about 1000 &#x3bc;m, and a height difference between the substrate and the edge ring is less than about (+/&#x2212;) 300 &#x3bc;m. The resistivity of the ring is less than about 50 Ohm-cm.

Universal process kit

Methods are disclosed for etching a substrate. The method includes preferentially coating cover ring relative other chamber components in the processing chamber, while under vacuum, and while a substrate is not present in the processing chamber. The substrate is subsequently etched the processing chamber. After etching, the interior of the processing chamber is cleaned after the substrate has been removed.

Minimization of ring erosion during plasma processes

The invention relates to a method of etching a layer of porous dielectric material, characterized in that the etching is performed in a plasma formed from at least one silicon-based gas mixed with oxygen (O) and/or nitrogen (N) so as to grow a passivation layer all along said etching, at least on flanks of the layer of porous dielectric material and wherein the silicon-based gas is taken from all the compounds of the type SiHfor which the ratio x/y is equal or greater than 0.3 or is taken from all the compounds of the following types: SiFand SiCl, where x is the proportion of silicon (Si) in the gas and y is the proportion of fluorine (F) or chlorine (Cl) or hydrogen (H) in the gas.

Method of etching a porous dielectric material

A method for manufacturing a resistive device, includes depositing a first electrically conductive layer on a substrate; forming an etching mask on the first conductive layer; etching the first conductive layer through the mask, such as to obtain a plurality of electrically conductive pillars separated from one another; and forming storage elements with variable electrical resistance at the tops of the electrically conductive pillars, such that each storage element is supported by one of the electrically conductive pillars, the step of forming the storage elements including the following operations depositing a first layer by non-collimated cathode sputtering at normal incidence relative to the substrate; and depositing a second layer on the first layer by cathode sputtering, the second layer including a first chemical species sputtered at an oblique incidence.

Method for manufacturing a resistive device for a memory or logic circuit

Embodiments include devices and methods for detecting particles, monitoring etch or deposition rates, or controlling an operation of a wafer fabrication process. In an embodiment, one or more micro sensors are mounted on wafer processing equipment, and are capable of measuring material deposition and removal rates in real-time. The micro sensors are selectively exposed such that a sensing layer of a micro sensor is protected by a mask layer during active operation of another micro sensor, and the protective mask layer may be removed to expose the sensing layer when the other micro sensor reaches an end-of-life. Other embodiments are also described and claimed.

Wafer processing equipment having exposable sensing layers

Embodiments described herein relate to methods for etching a substrate. Patterning processes, such as double patterning and quadruple patterning processes, may benefit from the embodiments described herein which include performing an inert plasma treatment to implant ions into a spacer material, performing an etching process on an implanted region of the spacer material, and repeating the inert plasma treatment and the etching process to form a predominantly flat top spacer profile. The inert plasma treatment process may be a biased process and the etching process may be an unbiased process. Various processing parameters, such as pressure, may be controlled to influence a desired spacer profile.

Cyclic oxide spacer etch process

Composite edge ring

The invention relates to the use of a ceramic of formula BaMInM'O(OH)where M represents at least one metal cation with an oxidation number II or III or a combination thereof, M&#x2032; represents at least one metal cation with an oxidation number III, IV, V or VI or a combination thereof, 0&#x2266;x&#x2266;1, 0&#x2266;y&#x2266;1, &#x3b4;&#x2266;2 and 0 &#x3c;&#x3b4;&#x2032;&#x2266;2, as solid proton-conducting electrolyte in an electrochemical device, in particular a fuel cell, an electrolytic cell, a membrane separating hydrogen from a gas mixture, or also a hydrogen detector, at an operating temperature of said electrochemical device preferably comprised between 200&#xb0; C. and 600&#xb0; C.

Electrochemical device comprising a proton-conducting ceramic electrolyte

A method is provided for forming spacers for a gate of a field effect transistor, the gate being situated above a layer of semiconductor material, including forming a layer of nitride covering the gate; modifying the layer by plasma implantation of light ions, having an atomic number equal or less than 10, in the layer in order to form a modified layer of nitride, the modifying being performed so as not to modify the layer of nitride over its entire thickness at flanks of the gate; and removing the modified layer of nitride by a selective wet or dry etching, of the modified layer relative to said layer of semiconductor material and relative to the non-modified layer at the flanks of the gate, without etching the layer of semiconductor material, wherein an entire length of the non-modified layer at the flanks remains after the selective wet or dry etching.

Method for forming spacers for a transistor gate

A microelectronic method for etching a layer to be etched, including: modifying the layer to be etched from a surface of the layer to be etched and over a depth corresponding to at least a portion of thickness of the layer to be etched to form a film, with the modifying including implanting light ions into the layer to be etched; and removing the film includes a selective etching of the film relative to at least one layer underlying the film.

Microelectronic method for etching a layer

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Meylan, France

Olivier Joubert