International Business Machines Corporation

Globalfoundries Inc.

Agere Systems Inc.

Samsung Electronics Co., Ltd.

Infineon Technologies Ag

Oliver Desmond Patterson

William J Cote

Yi Feng

Renee Tong Mo

Jin Ping Liu

Horatio Seymour Wildman

Brian W Messenger

Norbert Arnold

Ishtiaq Ahsan

Zhigang Song

Bradley J Albers

Kevin T Wu

Xing Zhou

Huilong Zhu

Christian Lavoie

Conal Eugene Murray

Randy William Mann

Robert L Wisnieff

Daniel Charles Kerr

Mark B Ketchen

Min-Chul Sun

Yunsheng Song

Eric C Harley

Yongchun Xin

Thomas A Wallner

Kevin McStay

Maryjane Brodsky

Jin Zheng Wallner

Edward Paul Martin, Jr

Thomas Craig Esry

Scott Jansen

Kourosh Nafisi

Shenzhi Yang

Peter Lin

Weihong Gao

Michael Scott Twiford

Min Chul Sun

David M Shuttleworth

Werner Weck

Gregory Brown

A method in which connectivity tests of integrated circuit structures in a die are performed. The connectivity tests are performed at a first level of the die. Potential defect locations are identified in the die indicating via locations susceptible to systematic failure due to via opens or via shorts. The potential defect locations are translated to via locations for a second level of the die. The second level is below the first level. After translating the hot spot, the second level is inspected for defects. The via locations on the first level are inspected for defects. All defects for the second level are translated to the via locations for the first level. A net trace of defects is created using prior level subtraction of the translated defects for the second level and the defects for the first level.

Apparatus for and method of net trace prior level subtraction

A method for designing, a structure, method of inspecting and a computer system for designing voltage contrast integrated circuit characterization. The design method includes selecting a design level of a mask design shapes file; selecting a region of the design level having an open region having no design shapes and an adjacent circuit region having circuit design shapes; selecting a sub-region of the circuit region adjacent to the open region; copying design shapes of the sub-region to generate a characterization cell identical to the sub-region; modifying the characterization cell to generate a passive voltage contrast characterization cell; and placing the passive voltage contrast characterization cell into the open region adjacent to the sub-region to generate a modified design level.

Voltage contrast characterization structures and methods for within chip process variation characterization

A semiconductor substrate inspection system includes an e-beam inspection system configured to deliver electrons to a specimen semiconductor substrate. A sensor is configured to detect reflected electrons that reflect off the surface of the specimen semiconductor substrate. An analysis unit is configured to determine a number of electrons received by the semiconductor substrate, and to determine at least one target region including at least one defect of the semiconductor substrate. A reference image module is in electrical communication with the analysis unit. The reference image module is configured to generate a first digital image having a plurality of pixels, and to adjust a gray-scale level of the pixels included in the target region based on the number electrons included in each pixel to generate a second digital image that excludes the at least one defect.

Method of inspecting a semiconductor substrate

A test structure of a semiconductor wafer includes a series of electrical units connected electrically in series output-to-input in an open loop configuration. The series of electrical units is configured to have alternating output voltages, such that each electrical unit is configured to output a voltage opposite an output voltage of a preceding electrical unit. Each electrical unit is configured to have an output voltage that alternates when an input voltage applied to a first electrical unit in the series of electrical units alternates.

Evaluating transistors with e-beam inspection

A method including forming a first test structure and a second test structure in electrical contact with an inner buried plate and an outer buried plate, respectively, where the first and second test structures each comprise a deep trench filled with a conductive material, and measuring the voltage of the inner buried plate and the outer buried plate immediately after the formation of a deep trench isolation structure, where the inner buried plate and the outer buried plate are positioned on opposite sides of the deep trench isolation structure.

Voltage contrast inspection of deep trench isolation

Test structures and method for detecting defects using the same. A probe-able voltage contrast (VC) comb test structure that includes first, second and third probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines, switching devices coupled with an end portion of each floating tine, and connecting the floating tines to the second probe pad, and the third probe pad being a control pad which controls the switching devices. A probe-able VC serpentine test structure that includes first, second, third and fourth probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines and each floating tine connected together between the second and third probe pads, switching devices connected to an end portion of each floating tine and connecting the floating tines to the second and third probe pads, and the fourth probe pad being a control pad which controls the switching devices.

Probe-able voltage contrast test structures

A system and method for improved voltage contrast inspection is disclosed. In one embodiment the temporal response to voltage contrast is considered to find an optimal acquisition time. In another embodiment, multiple optimal acquisition times are identified. The identified acquisition times are used in voltage contrast inspection of semiconductor fabrication, and are well-suited to SOI technology.

Inspection tool and methodology for three dimensional voltage contrast inspection

A static random access memory (SRAM) test structure includes a p-type source/drain implant region comprising contacts (CAs), wherein the CAs in the p-type source/drain implant region comprise a first plurality of bit line, ground, and node CAs, and wherein the CAs in the p-type source/drain implant region are grounded during an inspection of the SRAM test structure; and an ungrounded region, the ungrounded region being distinct from the p-type source/drain implant region and being ungrounded during the inspection of the SRAM test structure, the ungrounded region comprising contacts (CAs) and rectangular contacts (CArecs) comprising a second plurality of bit line, ground, and node CAs, and further comprising a first plurality of VCAs and rectangular contacts (CArecs), and wherein a CA or CArec in the ungrounded region is grounded during the inspection in the event of a short to a CA in the p-type source/drain implant region.

Static random access memory test structure

A semiconductor structure including a test structure for detection of a gap in a conductive layer of the semiconductor structure includes a semiconductor substrate; the test structure, the test structure being located on the semiconductor substrate, the test structure comprising a multilayer gate stack, wherein the multilayer gate stack includes a single conductive layer region including: a gate dielectric located on the semiconductor substrate; the conductive layer located on the gate dielectric; and an undoped amorphous silicon layer located on the conductive layer; and wherein the test structure is configured to detect the presence of the gap in the conductive layer.

Test structure for detection of gap in conductive layer of multilayer gate stack

A method of performing inspection alignment point selection for semiconductor devices includes importing, with a computer device, one or more semiconductor design files corresponding to an area of a semiconductor die; aligning a design taken from the one or more semiconductor design files with an image taken from a die of a semiconductor wafer; and selecting an alignment point and recording a portion of the design file corresponding to the alignment point as a master reference image.

Robust inspection alignment of semiconductor inspection tools using design information

Growing community of inventors

Poughkeepsie, NY, United States of America

Oliver Desmond Patterson