Applied Materials, Inc.

University of Florida Research Foundation, Incorporated

Glo Ab

Other

Olga Kryliouk

Yuriy Melnik

Tetsuya Ishikawa

Jie Su

Son Truong Nguyen

Anzhong Chang

David H Quach

Lily L Pang

Timothy J Anderson

Harsukhdeep S Ratia

Hidehiro Kojiri

Sang Won Kang

Tim Anderson

Linda T Romano

Nathan Fredrick Gardner

Sandeep Nijhawan

Ying-Lan Chang

Sungsoo Yi

Patrik Svensson

Tuoh-Bin Ng

Jie Cui

Giuliano Portilho Vescovi

Hyun Jong Park

Kee Chan Kim

Hua Chung

Lori D Washington

Brian Hayes Burrows

Michael Anthony Mastro

Dong Hyung Lee

Anand Vasudev

Bruce Chai

Jacob Grayson

Omar J Bchir

A method and apparatus for removing deposition products from internal surfaces of a processing chamber, and for preventing or slowing growth of such deposition products. A halogen containing gas is provided to the chamber to etch away deposition products. A halogen scavenging gas is provided to the chamber to remove any residual halogen. The halogen scavenging gas is generally activated by exposure to electromagnetic energy, either inside the processing chamber by thermal energy, or in a remote chamber by electric field, UV, or microwave. A deposition precursor may be added to the halogen scavenging gas to form a deposition resistant film on the internal surfaces of the chamber. Additionally, or alternately, a deposition resistant film may be formed by sputtering a deposition resistant metal onto internal components of the processing chamber in a PVD process.

Method of decontamination of process chamber after in-situ chamber clean

A semiconductor device, such as an LED, includes a plurality of first conductivity type semiconductor nanowire cores located over a support, a continuous second conductivity type semiconductor layer extending over and around the cores, a plurality of interstitial voids located in the second conductivity type semiconductor layer and extending between the cores, and first electrode layer that contacts the second conductivity type semiconductor layer.

Coalesced nanowire structures with interstitial voids and method for manufacturing the same

Aspects of the invention provide methods and devices. In one embodiment, the invention relates to the growing of nitride semiconductors, applicable for a multitude of semiconductor devices such as diodes, LEDs and transistors. According to the method of the invention nitride semiconductor nanopyramids are grown utilizing a CVD based selective area growth technique. The nanopyramids are grown directly or as core-shell structures.

Nanopyramid sized opto-electronic structure and method for manufacturing of same

A method of depositing a high quality low defect single crystalline Group III-Nitride film. A patterned substrate having a plurality of features with inclined sidewalls separated by spaces is provided. A Group III-Nitride film is deposited by a hydride vapor phase epitaxy (HVPE) process over the patterned substrate. The HVPE deposition process forms a Group III-Nitride film having a first crystal orientation in the spaces between features and a second different crystal orientation on the inclined sidewalls. The first crystal orientation in the spaces subsequently overgrows the second crystal orientation on the sidewalls and in the process turns over and terminates treading dislocations formed in the first crystal orientation.

Method of forming a group III-nitride crystalline film on a patterned substrate by hydride vapor phase epitaxy (HVPE)

Methods of epitaxy of gallium nitride, and other such related films, and light emitting diodes on patterned sapphire substrates, and other such related substrates, are described.

Formation of group III-V material layers on patterned substrates

A layered group III-nitride article includes a single crystal silicon substrate, and a highly textured group III-nitride layer, such as GaN, disposed on the silicon substrate. The highly textured group III-nitride layer is crack free and has a thickness of at least 10 &#x3bc;m. A method for forming highly textured group III-nitride layers includes the steps of providing a single crystal silicon comprising substrate, depositing a nanostructured InGaN (1&#x2267;x&#x2267;0) interlayer on the silicon substrate, and depositing a highly textured group III-nitride layer on the interlayer. The interlayer has a nano indentation hardness that is less than both the silicon substrate and the highly textured group III-nitride layer.

Group III-nitrides on Si substrates using a nanostructured interlayer

Techniques for crack-free growth of GaN, and related, films on larger-size substrates via spatially confined epitaxy are described.

Growth of group III-V material layers by spatially confined epitaxy

Embodiments disclosed herein generally relate to an HVPE chamber. The chamber may have two separate precursor sources coupled thereto to permit two separate layers to be deposited. For example, a gallium source and a separate aluminum source may be coupled to the processing chamber to permit gallium nitride and aluminum nitride to be separately deposited onto a substrate in the same processing chamber. The nitrogen may be introduced to the processing chamber at a separate location from the gallium and the aluminum and at a lower temperature. The different temperatures causes the gases to mix together, react and deposit on the substrate with little or no deposition on the chamber walls.

HVPE chamber hardware

HVPE precursor source hardware

Group III-nitrides on SI substrates using a nanostructured interlayer

Dome assembly for a deposition chamber

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Sunnyvale, CA, United States of America

Olga Kryliouk