Other

Hitachi, Ltd.

Hitachi Ulsi Systems Co., Ltd.

Hitachi Ulsi Engineering Corp.

Hitachi Hokkai Semiconductor Ltd.

Hitachi Instruments Engineering Co., Ltd.

Nozomu Matsuda

Kenichi Kuroda

Masahiro Moniwa

Masayuki Kojima

Kozo Watanabe

Atsushi Ogishima

Kiyonori Ohyu

Syunichi Hashimoto

Hiroyuki Uchiyama

Yoshiyuki Kaneko

Hiroki Soeda

Yasuhide Fujioka

Motoko Sawamura

A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodesare formed via a gate insulating filmon the main surface of a semiconductor substrate, and on side surfaces of each of the gate electrodes there is formed a first side wall spacercomposed of silicon nitride and a second side wall spacercomposed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holesandin a self-matching manner with respect to the first side wall spacersand connecting portion is formed connecting a conductorto a bit line BL. In addition, in the N channel MISFETs Qnand Qn, and in the P channel MISFET Qpin areas other than the DRAM memory cell area, high density N-type semiconductor areasandare formed, as well as a high density P-type semiconductor areais formed in a self-matching manner with respect to the second side wall spacers

Semiconductor integrated circuitry and method for manufacturing the circuitry

A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes are formed via a gate insulating film on the main surface of a semiconductor substrate , and on side surfaces of each of the gate electrodes there is formed a first side wall spacer composed of silicon nitride and a second side wall spacer composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes and in a self-matching manner with respect to the first side wall spacers and connecting portion is formed connecting a conductor to a bit line BL. In addition, in the N channel MISFETs Qn and Qn , and in the P channel MISFET Qp in areas other than the DRAM memory cell area, high density N-type semiconductor areas and are formed, as well as a high density P-type semiconductor area is formed in a self-matching manner with respect to the second side wall spacers

It is an object of the present invention to provide a technology of a semiconductor integrated circuitry that allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operated faster. In a method for manufacturing such a semiconductor integrated circuitry of the present invention, at first, gate electrodes are formed via a gate insulating film on the main surface of a semiconductor substrate , and on side surfaces of each of the gate electrodes is formed the first side wall spacer composed of silicon nitride and the second side wall spacer composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area are opened connecting holes and in a self-matching manner with respect to the first side wall spacers and are formed connecting portion connecting a conductor to a bit line BL. In addition, in the N channel MISFETs Qn and Qn , and in the P channel MISFET Qp in areas other than the DRAM memory cell area are formed high density N-type semiconductor areas and , as well as a high density P-type semiconductor area in a self-matching manner with respect to the second side wall spacers

Semiconductor integrated circuit device and method for manufacturing the same

A semiconductor memory device has memory cells provided at intersections between word line conductors and data line conductors. Each of the memory cells includes a cell selecting transistor and an information storage capacitor. The capacitor in each of the memory cells includes a first capacitor component formed over the control electrode of the transistor and a second capacitor component formed over a word line conductor which is adjacent to a word line conductor integral with the control electrode of the transistor. Each of the first and second capacitor components has a common electrode, a storage electrode and a dielectric film sandwiched therebetween, and the storage electrode is at a level higher than the common electrode in each of said first and second capacitor components. The storage electrodes of the first and second capacitor components are electrically connected with each other and with one of the semiconductor regions of the transistor. The other semiconductor region of the transistor is electrically connected with one of the data line conductors. Patterning of the storage electrodes of the first and second capacitor components is preferalbly effected by use of masks of a stripe pattern.

Semiconductor memory device including memory cells each having an

Growing community of inventors

Akishima, Japan

Nozomu Matsuda