Hitachi, Ltd.

Hitachi Microcomputer Engineering, Ltd.

Hatachi Ltd

Hitachi Device Eng. Co., Ltd.

Nozomi Horino

Akira Endo

Hisao Katto

June Sugiura

Yuji Arakawa

Yoshiharu Takeuchi

Yoji Nishio

Shigeru Shimada

Isamu Kobayashi

Yasuo Kaminaga

Akihiro Tomozawa

Shozo Hosoda

Kousaku Hirose

Osamu Tsuchiya

Yoshiaki Yoshiura

Yoshihiko Yamamoto

Yoku Kaino

In order to present a basic cell of a master slice type LSI having a high memory density and a high speed logic circuitry, a basic cell is composed of each pair of the PMOS 1, NMOS 4, PMOS 7, and NMOS 10, and three contact holes--besides the contact holes 17, as the contact holes within the MOS channel width W of each MOS, that are connected to the GND power lines 51 and 53, or the Vcc power lines 50 and 52--are formed in the direction perpendicular to each of the power lines. Additionally, in order to present a semiconductor integrated device having a static type RAM that has realized with its simple structure a shortening of the memory cycle, a RAM is constructed by having memory cells, in which each is composed of a pair of transfer MOSFETs, which both of the MOSFETs are turned on during the write-in operation and one of the MOSFETs is turned on during the read-out operation, is located in between a complementary data line and an input/output node that has a complementary relationship with an information storage part comprised by a pair of inverter circuits in which the inputs and outputs are mutually cross-connected. By constructing in this way, it becomes possible to speed up the write-in operation with accuracy by having a complementary write-in signal received from a pair of the complementary lines during the read-out operation, and it becomes possible to obtain read-out signals rapidly and to prevent write-in errors caused by the pre-read-out potential of the data line because the information storage part is connected only to one of the data lines through one of the transfer gates during the read-out operation.

Semiconductor gate array device

A semiconductor memory device having wiring formed next to word lines at the extreme ends of the memory cell arrays or next to word lines of the dummy cell arrays, in order to prevent such word lines from breaking or from becoming deformed. The wiring is irrelevant to the circuit operation, but is provided with a fixed potential, and is formed through the steps of forming the word lines. The wiring makes the processing conditions applied to the neighboring word lines the same as the processing conditions applied to other word lines.

Method of making a semiconductor memory device

Semiconductor memory device with additional conductive line to prevent

Herein disclosed is a process of fabricating a semiconductor integrated circuit device, in which there is formed between a conductive layer prepared by covering a polycrystalline silicon layer with either a layer containing a refractory metal of high melting point, i.e., a refractory metal layer or a silicide layer of the refractory metal and a first insulating film made of phosphosilicate glass flowing over said conductive layer containing the refractory metal, a second insulating film preventing the layer containing a refractory metal from peeling from the polycrystalline silicon layer by the glass flow. The second insulating film is formed by deposition to have a thickness not smaller than a predetermined value.

Process of fabricating a semiconductor insulated circuit device having a

Semiconductor memory device with means to prevent word line breakage

Growing community of inventors

Higashiyamato, Japan

Nozomi Horino