Globalfoundries Inc.

Norman Chen

Yuyang Sun

Chidam Kallingal

Shaowen Gao

Jian Liu

Randy W Mann

Sonia Ghosh

Hongxin Zhang

Mahbub Rashed

Marc Laurent Tarabbia

Paul Willard Ackmann

Anurag Mittal

Tuhin Guha Neogi

Matthew Thomas Herrick

Ayman Hamouda

Sohan Singh Mehta

Nader Magdy Hindawy

Shyam Pal

Jeong Soo Kim

Scott Goad

Feng Wang

Chang A Wang

A method disclosed herein includes: converting an image of a manufactured circuit to a plurality of representative contours, the plurality of representative contours corresponding to printed features in the manufactured circuit; generating a risk inventory for the manufactured circuit based on the plurality of representative contours, the risk inventory being configured to identify at least one process sensitive geometry (PSG) in the manufactured circuit; generating a common process window (CPW) for the manufactured circuit based on the plurality of representative contours and the risk inventory, the CPW being indicative of manufacturing reliability of each feature in the manufactured circuit; and generating instructions to adjust a manufacturing tool for creating the manufactured circuit, based on the generated CPW.

Generating risk inventory and common process window for adjustment of manufacturing tool

A method of creating an optical proximity correction (OPC) model and assessing the model through optical rule checking (ORC) includes the introduction of post-integration, i.e., post-metallization data. High density critical dimension scanning electron microscopy and backscattered electron scanning electron microscopy from a metallized structure are used during development and verification of the model to accurately predict post-integration behavior.

Methodology for post-integration awareness in optical proximity correction

Methods for forming a semiconductor layer, such as a metal1 layer, having minimum width features separated by a distance greater than a minimum pitch, and the resulting devices are disclosed. Embodiments may include determining a first shape and a second shape having a minimum width within a semiconductor layer, wherein a distance between the first shape and the second shape is greater than a minimum pitch, determining an intervening shape between the first shape and the second shape, and designating a dummy shape within the intervening shape, wherein the dummy shape is at the minimum pitch from the first shape.

Device resulting from printing minimum width semiconductor features at non-minimum pitch

Methods for retargeting a circuit design layout for a multiple patterning lithography process and for fabricating a semiconductor device are provided. In an exemplary embodiment, a computer-executed method for retargeting a circuit design layout for a multiple patterning lithography process is provided. The method includes decomposing a circuit design layout file to produce decomposed layout files in a computer. Each decomposed layout file is associated with a respective mask for use in the multiple patterning lithography process. The method includes preparing retargeted layout files in the computer by retargeting selected decomposed layout files based on photolithography limitations specific to each selected decomposed layout file to produce retargeted layout files. Also, the method includes determining in the computer that a combination of layout files includes a spacing conflict. The method further includes resolving the spacing conflict in the computer by modifying the layout file or layout files causing the spacing conflict.

Methods for retargeting circuit design layouts and for fabricating semiconductor devices using retargeted layouts

Printing minimum width semiconductor features at non-minimum pitch and resulting device

Methods are provided for fabricating semiconductor integrated circuits including isolated trench features. In one embodiment, a method includes providing a semiconductor substrate with an overlying process layer. A trench pattern to be etched into the process layer is determined and that trench pattern is decomposed into first and second patterns, the second pattern including an isolated trench. First and second lithographic masks are formed to implement the first and second patterns, the second mask implementing the second pattern, the isolated trench, and a plurality of density balancer patterns symmetrically positioned with respect to the isolated trench. A first resist layer is patterned with the first lithographic mask and the process layer is etched with the first resist layer. A second resist layer is patterned with the second lithographic mask and the process layer is etched with the second resist layer to implement the required trench pattern in the process layer.

Method for fabricating a semiconductor integrated circuit with a litho-etch, litho-etch process for etching trenches

A method includes receiving a design layout file for an integrated circuit device in a computing apparatus. The design layout file specifies dimensions of a plurality of features. The design layout file is decomposed to a plurality of colored layout files, each colored layout file representing a particular reticle in a multiple patterning process. Each of the colored layout files is retargeted separately in the computing apparatus to generate a plurality of retargeted colored layout files. Retargeting each of the colored layout files includes increasing dimensions of a first plurality of features based on spacings between the first plurality of features and adjacent features. The retargeted layout files are combined to generate a combined layout file. Features in the combined layout file are retargeted in the computing apparatus to increase dimensions of a second plurality of features based on spacings between the second plurality of features and adjacent features.

Retargeting semiconductor device shapes for multiple patterning processes

A method includes electrically connecting a plurality of cells of a standard cell library to a power rail. A contact area is deposited to connect a first active area and a second active area of a cell of a plurality cells. The first area and the second area are located on opposite sides of the rail and electrically connected to different drains. The contact area is electrically connected to the power rail using a via. The contact area is masked to remove a portion of the contact area to electrically separate the first active are from the second active area.

Power rail layout for dense standard cell library

One illustrative method disclosed herein involves identifying an overall target pattern comprised of at least one hole-type feature, decomposing the overall target pattern into at least a first sub-target pattern and a second sub-target pattern, wherein the first sub-target pattern and the second sub-target pattern each comprise at least one common hole-type feature, generating a first set of mask data information corresponding to the first sub-target pattern, and generating a second set of mask data information corresponding to the second sub-target pattern.

Multiple patterning process for forming trenches or holes using stitched assist features

Embodiments of the invention provide approaches for optimizing illumination and polarization for advanced optical lithography. Specifically, an illumination pupil plane of an illumination source is bisected into a plurality of elements. Preferred elements of the illumination pupil plane are selected for a set of integrated circuit (IC) design features. An imaging performance of the set of IC design features for the preferred elements is evaluated at different polarization states to determine an optimal illumination and polarization condition for each IC design feature. Imaging performance of the combined IC design features, evaluated at various optimal illumination and polarization outcomes synthesized at different intensity ratios, is reviewed against a set of design tolerance requirements to finalize optical illumination and polarization conditions for the entire IC design. An optimal illumination and polarization solution is identified for an off-contact pattern with a plurality of sub-resolution assisted features connecting line-line-end portions of main mask features.

Use of polarization and composite illumination source for advanced optical lithography

An optical proximity correction (OPC) method for photolithography applications can be utilized to reduce the processing time, cost, and post-OPC file size associated with conventional methods. The OPC method provides a target layout pattern that represents a corresponding mask pattern for a photolithography mask, and aligns the target layout pattern relative to a suitably dimensioned fragmentation grid. Then, at least one feature of the target layout pattern is fragmented using the fragmentation grid. Thereafter, a fragment data set is generated in response to the grid-based fragmentation of the target layout pattern.

Grid-based fragmentation for optical proximity correction in photolithography mask applications

Methods for fabricating a semiconductor device and a lithographic mask of use in that method are provided for. The lithographic mask comprises an optically transparent substrate, an attPSM pattern overlying the optically transparent substrate, and a phase shifted optically transparent portion adjacent to and aligned with an edge of the attPSM pattern.

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Poughkeepsie, NY, United States of America

Norman Chen