Infineon Technologies Ag

Norliza Morban

Chau Fatt Chiang

Cher Hau Danny Koh

Khay Chwan Andrew Saw

Si Hao Vincent Yeo

Chan Lam Cha

Khay Chwan Saw

Yong Chern Poh

Wern Ken Daryl Wee

Fortunato Lopez

Thorsten Meyer

Swee Kah Lee

Thorsten Hinderer

Chee Hong Lee

Sock Chien Tey

Mei Yong Wang

Chee Hoe Mak

Ryan Ross Alinea

Yun Yann Ng

Desmond Jenn Yong Loo

Ying Dieh Cheong

Swee Kat Lee

Eric Lopez Bonifacio

A package includes a dielectric carrier, an electronic component mounted on the dielectric carrier, and an encapsulant encapsulating at least part of the dielectric carrier and the electronic component. Corresponding methods of manufacturing the package are also described.

Semiconductor packages and methods for manufacturing thereof

A method of forming a semiconductor package includes providing a metal baseplate having a base section and a plurality of metal posts, the base section being a planar pad of substantially uniform thickness, the plurality of metal posts each extending up from a planar upper surface of the base section, mounting a semiconductor die on the upper surface of the metal baseplate, forming an encapsulant body of electrically insulating mold compound on the upper surface of the base section, electrically connecting terminals of the semiconductor die to the metal posts, and removing the base section so as to form package contacts from the metal posts at a first surface of the encapsulant body.

Semiconductor package with metal posts from structured leadframe

A semiconductor package includes a semiconductor die, an encapsulation encapsulating the semiconductor die, the encapsulation having a first side and an opposing second side, a plurality of contact pads for electrically contacting the semiconductor die, the contact pads being arranged on the first side of the encapsulation, and a plurality of inspection holes arranged in communication with the contact pads and extending from the first side to the second side, such that solder joints on the first side of the encapsulation are optically inspectable using the inspection holes viewed from the second side of the encapsulation.

Semiconductor package and method for fabricating a semiconductor package

An electronic circuit includes a first packaged semiconductor device having a first semiconductor die including a first terminal, a first electrically conductive lead that is electrically connected to the first terminal, and a first electrically insulating mold compound that encapsulates the first semiconductor die and exposes an end portion of the first lead at an outer surface of the first mold compound. A conductive track is formed in the outer surface of the first mold compound.

Formation of conductive connection tracks in package mold body using electroless plating

A lead frame includes a first die paddle, a second die paddle, a first lead, a second lead, and a third lead. The first lead is coupled to a first side of the first die paddle. The second lead is coupled to a second side of the first die paddle opposite to the first side of the first die paddle. The third lead is coupled to a first side of the second die paddle. At least one of the first lead, the second lead, and the third lead is coupled to the corresponding die paddle via a zigzag shaped tie bar.

Lead frames for semiconductor packages

A first packaged semiconductor device is provided. The first packaged semiconductor device includes a first semiconductor die having a first terminal, a first electrically conductive lead that is electrically connected to the first terminal, and a first electrically insulating mold compound that encapsulates the first semiconductor die and exposes an end portion of the first lead at an outer surface of the first mold compound. A conductive track is formed in the outer surface of the first mold compound. Forming the conductive track includes activating a portion of the outer surface of the first mold compound for an electroless plating process, and performing the electroless plating process so as to form an electrically conductive material only within the activated portion of the outer surface of the first mold compound.

A universal lead frame for semiconductor packages includes a solid lead frame sheet comprising an electrically conductive material and a plurality of columns etched into the lead frame sheet and distributed with a predetermined lead pitch so that the universal lead frame has a solid first main side opposite the columns and a patterned second main side opposite the first main side. A method of manufacturing the universal lead frame includes providing a solid lead frame sheet of an electrically conductive material and etching a plurality of columns into the lead frame sheet so that the columns are distributed with a predetermined lead pitch and the universal lead frame has a solid first main side opposite the columns and a patterned second main side opposite the first main side. A method of manufacturing molded semiconductor packages using the universal lead frame is also provided.

Universal lead frame for flat no-leads packages

Growing community of inventors

Melaka, Malaysia

Norliza Morban