Kepler Computing Inc.

Intel Corporation

Noriyuki Sato

Sasikanth Manipatruni

Tanay Gosavi

Amrita Mathuriya

Rajeev Kumar Dokania

Niloy Mukherjee

Somilkumar J Rathi

Debo Olaosebikan

Mauricio Manfrini

Pratyush Pandey

Kaan Oguz

Kevin O'Brien

Jason Y Wu

Hui Jae Yoo

Ian A Young

Christopher J Wiegand

Angeline Smith

Benjamin Buford

Rafael Rios

Tofizur Rahman

Abhishek A Sharma

James David Clarkson

Van H Le

Sarah Atanasov

Ramamoorthy Ramesh

Gary Allen

Gabriel Antonio Paulius Velarde

Matthew V Metz

Mark L Doczy

Kevin Lai Lin

Charles C Kuo

Bernhard Sell

Manish Chandhok

Travis W LaJoie

Pei-Hua Wang

Chieh-Jen Ku

Nafees Kabir

Fnu Atiquzzaman

Zeying Ren

Debraj Guhabiswas

Christopher J Jezewski

Chia-Ching Lin

Eungnak Han

Elliot Tan

Carl H Naylor

Gurpreet Singh

Arnab Sen Gupta

Mustansir Yunus Mukadam

Michael Christenson

Abel Fernandez

Ram K Krishnamurthy

Dmitri E Nikonov

Elijah V Karpov

Charles Henry Wallace

Leonard P Guler

Gregory Kengho Chen

James M Blackwell

Paul Anton Nyhus

Phil Knag

Huseyin Ekin Sumbul

Ramanan Chebiam

Miriam Ruth Reshotko

Tristan A Tronic

David N Shykind

Jeffery D Bielefeld

James Pellegren

Emily Walker

Jinnie Aloysius

Jiun-Ruey Chen

Jonathan Laib

Gobind Bisht

Maria Isabel Perez

Brian S Doyle

Rami Hourani

John J Plombon

Justin Brockman

Md Tofizur Rahman

Pramod Kolar

Tobias Brown-Heft

Thoe Michaelos

Chieh-jen Ku

Atm G Sarwar

Rohan Patil

Ben Buford

Jason Peck

Saskikanth Manipatruni

Erik Unterborn

Ahmad Tavakoli

A method of fabricating a device comprises forming a multi-layer stack above a first substrate, where multi-layer stack includes a non-linear polar material. In at least one embodiment, method further includes forming a first conductive layer on multi-layer stack and annealing multi-layer stack. A transistor is formed above a second substrate. In at least one embodiment, method also includes forming a second conductive layer above electrode structure and bonding first conductive layer with second conductive layer. After bonding, method includes removing at least a portion of first substrate patterning multi-layer stack to form a memory device.

Method of integrating a capacitor including a non-linear polar material with a transistor through wafer bonding

A device structure comprises a first conductive interconnect, an electrode structure on the first conductive interconnect, an etch stop layer laterally surrounding the electrode structure; a plurality of memory devices above the electrode structure, where individual ones of the plurality of memory devices comprise a dielectric layer comprising a perovskite material. The device structure further comprises a plate electrode coupled between the plurality of memory devices and the electrode structure, where the plate electrode is in direct contact with a respective lower most conductive layer of the individual ones of the plurality of memory devices. The device structure further includes an insulative hydrogen barrier layer on at least a sidewall of the individual ones of the plurality of memory devices; and a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on a respective one of the individual ones of the plurality of memory devices.

Gate coupled non-linear polar material based capacitors for memory and logic

A pocket integration for high density memory and logic applications and methods of fabrication are described. While various embodiments are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For example, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.

Method of fabricating memory devices using pocket integration

Methods of fabricating planar capacitors on a shared plate electrode

A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.

Passivation layers for thin film transistors

Capacitor devices with shared electrode and methods of fabrication

Described herein is a memory sensing scheme that improves noise margin. In at least one embodiment, one or more circuitries are described that are coupled to a bit-cell, wherein the bit-cell is coupled to a plate-line and a bit-line, wherein the one or more circuitries are to sense a bit-value stored in the bit-cell based, at least in part, on a first floating charge on a plate-line and a second floating charge on a bit-line.

Apparatus and method to improve sensing noise margin in a non-linear polar material based bit-cell

Drain coupled non-linear polar material based capacitors for memory and logic

Methods of fabricating trench capacitors on a shared plate electrode

Described herein is a memory bit-cell that results in lower leakage and higher sensing margin. In at least one embodiment, a memory bit-cell comprises a plurality of capacitors, wherein an individual capacitor is coupled to a node and an individual plate-line. In at least one embodiment, memory bit-cell comprises a first transistor coupled to the node. In at least one embodiment, memory bit-cell comprises a second transistor coupled in series with the first transistor, wherein the second transistor is coupled to a bit-line, wherein the first transistor or the second transistor is controllable by a word-line, and wherein the word-line is parallel to the individual plate-line.

Non-linear polar material based multi-capacitor high density bit-cell

Integration of 2T-C for memory and logic applications

Planar capacitors with shared electrode and methods of fabrication

A method of fabricating a system includes fabricating a plurality of transistors and coupling a forming a bridge structure connected between a gate contact of a first transistor with a drain contact of a second transistor. The method further includes fabricating a multi-level memory structure including capacitors that comprise a ferroelectric material or a paraelectric material. The capacitors within a given level are coupled together by a plate electrode. The method further includes forming a signal electrode coupled with the plate electrode.

Stacked capacitors with shared electrodes and methods of fabrication

A memory is described having a plurality of bit-cells organized in a row or column. An individual bit-cell of the plurality of bit-cells includes an access transistor and a plurality of capacitors. A word-line is positioned under the access transistor, wherein the access transistor is controllable by the word-line, whereas the plurality of capacitors is positioned above the access transistor. The individual bit-cell has an individual boundary which substantially abuts a neighboring bit-cell in the row or column such that there is no dummy bit-cell between individual bit-cell and the neighboring bit-cell.

Memory array with buried or backside word-line

Method of fabricating transistors and stacked planar capacitors for memory and logic applications

Growing community of inventors

Hillsboro, OR, United States of America

Noriyuki Sato