Kepler Computing Inc.

Intel Corporation

Noriyuki Sato

Sasikanth Manipatruni

Tanay Gosavi

Amrita Mathuriya

Rajeev Kumar Dokania

Niloy Mukherjee

Somilkumar J Rathi

Debo Olaosebikan

Mauricio Manfrini

Pratyush Pandey

Kaan Oguz

Kevin O'Brien

Hui Jae Yoo

Jason Y Wu

Ian A Young

Christopher J Wiegand

Angeline Smith

Benjamin Buford

Rafael Rios

Tofizur Rahman

James David Clarkson

Abhishek A Sharma

Van H Le

Sarah Atanasov

Matthew V Metz

Kevin Lai Lin

Ramamoorthy Ramesh

Manish Chandhok

Gary Allen

Gabriel Antonio Paulius Velarde

Mark L Doczy

Charles C Kuo

Bernhard Sell

Travis W LaJoie

Nafees Kabir

Debraj Guhabiswas

Christopher J Jezewski

Carl H Naylor

Pei-Hua Wang

Chieh-Jen Ku

Fnu Atiquzzaman

Zeying Ren

Michael Christenson

Abel Fernandez

Elijah V Karpov

Chia-Ching Lin

James M Blackwell

Eungnak Han

Elliot Tan

Ramanan Chebiam

Miriam Ruth Reshotko

Tristan A Tronic

Jeffery D Bielefeld

Gurpreet Singh

Arnab Sen Gupta

Mustansir Yunus Mukadam

Jiun-Ruey Chen

Ram K Krishnamurthy

Dmitri E Nikonov

Charles Henry Wallace

Leonard P Guler

Gregory Kengho Chen

Paul Anton Nyhus

Phil Knag

Huseyin Ekin Sumbul

David N Shykind

James Pellegren

Emily Walker

Jinnie Aloysius

Jonathan Laib

Gobind Bisht

Maria Isabel Perez

Brian S Doyle

Biswajeet Guha

Rami Hourani

John J Plombon

Justin Brockman

Md Tofizur Rahman

Pramod Kolar

Thoe Michaelos

Tobias Brown-Heft

Chieh-jen Ku

Atm G Sarwar

Rohan Patil

Ben Buford

Jason Peck

Saskikanth Manipatruni

Erik Unterborn

Ahmad Tavakoli

IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

Subtractively patterned interconnect structures for integrated circuits

An integration process including an etch stop layer for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.

Integrating embedded memory with logic interconnects

A method of fabricating a device comprises forming a multi-layer stack above a first substrate, where multi-layer stack includes a non-linear polar material. In at least one embodiment, method further includes forming a first conductive layer on multi-layer stack and annealing multi-layer stack. A transistor is formed above a second substrate. In at least one embodiment, method also includes forming a second conductive layer above electrode structure and bonding first conductive layer with second conductive layer. After bonding, method includes removing at least a portion of first substrate patterning multi-layer stack to form a memory device.

Method of forming capacitors through wafer bonding

Method of integrating a capacitor including a non-linear polar material with a transistor through wafer bonding

A device structure comprises a first conductive interconnect, an electrode structure on the first conductive interconnect, an etch stop layer laterally surrounding the electrode structure; a plurality of memory devices above the electrode structure, where individual ones of the plurality of memory devices comprise a dielectric layer comprising a perovskite material. The device structure further comprises a plate electrode coupled between the plurality of memory devices and the electrode structure, where the plate electrode is in direct contact with a respective lower most conductive layer of the individual ones of the plurality of memory devices. The device structure further includes an insulative hydrogen barrier layer on at least a sidewall of the individual ones of the plurality of memory devices; and a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on a respective one of the individual ones of the plurality of memory devices.

Gate coupled non-linear polar material based capacitors for memory and logic

A pocket integration for high density memory and logic applications and methods of fabrication are described. While various embodiments are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For example, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.

Method of fabricating memory devices using pocket integration

Methods of fabricating planar capacitors on a shared plate electrode

A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.

Passivation layers for thin film transistors

Capacitor devices with shared electrode and methods of fabrication

Described herein is a memory sensing scheme that improves noise margin. In at least one embodiment, one or more circuitries are described that are coupled to a bit-cell, wherein the bit-cell is coupled to a plate-line and a bit-line, wherein the one or more circuitries are to sense a bit-value stored in the bit-cell based, at least in part, on a first floating charge on a plate-line and a second floating charge on a bit-line.

Apparatus and method to improve sensing noise margin in a non-linear polar material based bit-cell

Drain coupled non-linear polar material based capacitors for memory and logic

Methods of fabricating trench capacitors on a shared plate electrode

Described herein is a memory bit-cell that results in lower leakage and higher sensing margin. In at least one embodiment, a memory bit-cell comprises a plurality of capacitors, wherein an individual capacitor is coupled to a node and an individual plate-line. In at least one embodiment, memory bit-cell comprises a first transistor coupled to the node. In at least one embodiment, memory bit-cell comprises a second transistor coupled in series with the first transistor, wherein the second transistor is coupled to a bit-line, wherein the first transistor or the second transistor is controllable by a word-line, and wherein the word-line is parallel to the individual plate-line.

Non-linear polar material based multi-capacitor high density bit-cell

Integration of 2T-C for memory and logic applications

Planar capacitors with shared electrode and methods of fabrication

Growing community of inventors

Hillsboro, OR, United States of America

Noriyuki Sato