Oki Electric Industry Co., Ltd.

Kabushiki Kaisha Toshiba

Oki Semiconductor Co., Ltd.

Norio Hirashita

Takashi Ichimori

Toshiyuki Nakamura

Satoshi Ikeda

Naoharu Sugiyama

Tsutomu Tezuka

Minoru Saito

Yasuhiro Fukuda

Ikuo Kurachi

Naokatsu Ikegami

Hidetsugu Uchida

Yutaka Kamata

Mitsuhiro Matsuo

Guo-lin Liu

Masayuki Kobayakawa

Fumitaka Yokoyama

Izumi Aikawa

Tetsuhiko Sugahara

A semiconductor device includes diffusion layers formed in a SOI layer under a side-wall, a channel formed between the diffusion layers, silicide layers sandwiching the diffusion layers wherein interface junctions between the diffusion layers and the silicide layers are () silicon planes.

Semiconductor device having silicide layer completely occupied amorphous layer formed in the substrate and an interface junction of (111) silicon plane

A method of manufacturing a semiconductor device. In the method, a substrate is prepared, which includes a buried oxide film and a SiGe layer formed on the buried oxide film. Then, heat treatment is performed on the substrate at a temperature equal to or lower than a first temperature, to form a protective oxide film on a surface of the SiGe layer. Next, the substrate having the protective oxide film is heated in a non-oxidizing atmosphere to a second temperature higher than the first temperature. Further, heat treatment is performed on the substrate thus heated, in an oxidizing atmosphere at a temperature equal to or higher than the second temperature, to form oxide the SiGe layer, make the SiGe layer thinner and increasing Ge concentration in the SiGe layer, thus forming a SiGe layer having the increased Ge concentration.

Semiconductor device and method of manufacturing the same

A field effect transistor having metallic silicide layers is formed in a semiconductor layer on an insulating layer of an SOI substrate. The metallic silicide layers are composed of refractory metal and silicon. The metallic silicide layers extend to bottom surfaces of source and drain regions. A ratio of the metal to the silicon in the metallic silicide layers is X to Y. A ratio of the metal to the silicon of metallic silicide having the lowest resistance among stoichiometric metallic silicides is X0 to Y0. X, Y, X0 and Y0 satisfy the following inequality: (X/Y)&#x3e;(X0/Y0).

Structure of a field effect transistor having metallic silicide and manufacturing method thereof

A field effect transistor having metallic silicide layers is formed in a semiconductor layer on an insulating layer of an SOI substrate. The metallic silicide layers are composed of refractory metal and silicon. The metallic silicide layers extend to bottom surfaces of a source and a drain regions. A ratio of the metal to the silicon in the metallic silicide layers is X to Y. A ratio of the metal to the silicon of metallic silicide having the lowest resistance among stoichiometaric metallic silicides is Xto Y. X, Y, Xand Ysatisfy the following inequity: (X/Y)&#x3e;(X/Y).

An impurity is ion-implanted with a silicon nitride film formed on a silicon substrate as a mask film to form a source/drain layer of a MOS transistor. Heat treatment for activating the impurity is done as it is without removing the silicon nitride film to thereby produce heat treatment-based stress between the silicon nitride film and the silicon substrate.

Method of manufacturing semiconductor device

A heat treatment for diffusing impurity ions implanted into a silicon layer is performed at a heat treatment temperature which is less than an aggregation temperature of the silicon layer. A thermal aggregation of the silicon layer can be inhibited, thereby reducing a silicon deficiency of the silicon layer.

Method of manufacturing a semiconductor device

A device isolation region made up of a silicon oxide film, which is perfectly isolated up to the direction of the thickness of an SOI silicon layer, and an activation region of the SOI silicon layer, whose only ends are locally thinned, are formed on an SOI substrate. A source diffusion layer and a drain diffusion layer of a MOS field effect transistor in the activation region are provided so that according to the silicidization of the SOI silicon layer subsequent to the formation of a high melting-point metal, a Schottky junction is formed only at each end of the activation region and a PN junction is formed at a portion other than each end thereof.

SOI MOS field effect transistor and manufacturing method therefor

A protective layer is formed on a metallic silicide layer prior to a heat treatment for reducing a resistance of the metallic silicide layer. As a result, vertical growing of crystallization in the metallic silicide layer is restrained by the protective layer during the heat treatment. Moreover, the crystallization in the metallic silicide layer easily grows along the protective layer. Therefore, evenness of the metallic silicide layer can be maintained.

Method for fabricating a semiconductor device having a metallic silicide layer

In a semiconductor manufacturing apparatus, a semiconductor substrate ion-implanted with an ion species is heated and thereby raised in temperature under vacuum. At this time, a partial pressure of a gas released from the semiconductor substrate is measured by a quadrupole mass spectrometer. Further, a change in partial pressure with time is observed and compared with a pre-measured release characteristic, whereby the temperature of the semiconductor substrate is corrected.

Method of correcting temperature of semiconductor substrate

In order to achieve a method for analyzing the compositional distribution of deposited film adhering to the internal surface of a contact hole having a diameter in the deep submicron order, primary ions 18 are radiated into the surface 12a of an insulating film 12 where the contact hole 14 is formed to generate secondary ions 20. The primary ions are radiated into the surface of the insulating film from a constant diagonal direction. Then, mass spectrometry is performed on the resulting secondary ions to detect the compositional distribution of the deposited film 16 formed at the internal surface of the contact hole. Thus, the compositional distribution of the deposited film is ascertained over the depth-wise direction of the contact hole.

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Tokyo, Japan

Norio Hirashita