Hitachi, Ltd.

Showa Denko K.k.

Norikazu Hashimoto

Masaharu Kubo

Kiyoo Itoh

Ryoichi Hori

Shigeru Nishimatsu

Yasunari Umemoto

Yoshio Sakai

Toshiaki Masuhara

Kiichi Ueyanagi

Susumu Takahashi

Shoji Shukuri

Toshio Sasaki

Tokuo Kure

Takehisa Hayashi

Shinichi Tachi

Osamu Minato

Yoshifumi Kawamoto

Yasuo Wada

Hideo Sunami

Hiroshi Kawakami

Yuichi Ono

Noboru Masuda

Minoru Nagata

Yasuhiro Shiraki

Toshiyuki Usagawa

Hisao Katto

Nobuo Kotera

Hirotoshi Tanaka

Akihiro Takanashi

Junji Shigeta

Hisashi Maejima

Shuji Sugiyama

Mikio Ashikawa

Shin-ichi Muramatsu

Mitsumasa Koyanagi

Akihiro Tomozawa

Kikuo Douta

Hiroshi Yanazawa

Tsuyoshi Takaichi

Nobutoshi Matsunaga

A field effect transistor formed on a semi-insulator or compound semiconductor substrate comprises a first semiconductor layer forming a source region, a drain region and a channel layer, and a second semiconductor layer having a reverse conduction type to that of the first semiconductor layer. The second semiconductor layer is doped so that it will be totally depleted. Therefore, a portion of the second semiconductor layer adjacent to the substrate will remain conductive. The field effect transistor with this structure prevents the short channel effect and the soft error due to .alpha.-particles. A threshold voltage control arrangement is also provided using the feature of a control electrode coupled to the second semiconductor layer and a feedback arrangement.

Field effect transistor

An FET structure with improved .alpha.-particle immunity or soft error immunity particularly provided in a semi-insulating substrate. This structure includes some layer which can prevent both electrons and holes generated in a substrate by the incidence of .alpha.-particles from being injected into the FET.

Field effect transistor with alpha particle protection

A semiconductor device and method of manufacturing the same. The device comprises a first n-type semiconductor layer and a second undoped semiconductor layer between which a hetero-junction is formed, and a third p-type embedded semiconductor layer, a gate metal formed without the exposure to air immediately after the third, second and first semiconductor layer are successively formed, and an external electrode connected with the third p-type embedded semiconductor layer, capable of controlling the carriers in the neighborhood of the hetero-junction. This semiconductor device greatly improves the controllability of the threshold voltage thereof, and provides the gate electrodes of good quality.

Semiconductor device and manufacturing method of the same

A dry-etching gas suitable for selective etching of silicon nitride and a process for selectively dry-etching silicon nitride with the dry-etching gas are disclosed. Silicon nitride can be dry-etched with a higher selectivity or at a higher etching rate than silicon dioxide and silicon, and a process for fabricating semi-conductor devices can be simplified and devices with a novel structure can be realized.

Gas for selectively etching silicon nitride and process for selectively

A pattern exposing apparatus comprising means for projecting a semiconductor device mask pattern onto the photoresist layer coated on a semiconductor substrate, and means for projecting an identification mark which is specific to each substrate onto a part of the photoresist layer.

Pattern exposing apparatus

A first semiconductor circuit element including a first electrode is formed on a semiconductor substrate, an inter-layer insulating layer for insulating the first electrode is formed on the first electrode, and a first penetrating opening is provided in a part of the inter-layer insulating layer. Subsequently, a step of forming a second semiconductor circuit element is carried out, this step including a step of forming a second electrode so that at least a part thereof may overlie the inter-layer insulating layer at an area other than the first penetrating opening. Further, a subsidiary interconnection conductive layer is buried into the first opening. Another insulating layer is formed on the structure thus formed, whereupon second and third penetrating openings are respectively provided in the insulating layer over the second electrode and the interconnection subsidiary conductive layer. First and second interconnection conductors are respectively buried into the second and third penetrating openings. The first electrode is conductively connected with the second interconnection conductor in the third opening via the subsidiary interconnection conductive layer in the first opening. The second electrode is conductively connected with the first interconnection conductor in the second opening.

Semiconductor device with multi-layered electrodes

A semiconductor device including at least a resistance element formed of polycrystalline silicon having a high resistivity. An electrode is provided on the high resistance polycrystalline silicon region with a silicon dioxide film and a silicon nitride film being interposed therebetween. The electrode is coupled to the ground potential. In this manner, high stability is obtained in the behavior of the resistance element inasmuch as the formation of a parasitic MOS device under said high resistance region is suppressed, and the threshold voltage of any such MOS device is made raised.

Semiconductor device

A first semiconductor circuit element including a first electrode is formed on a semiconductor substrate, an insulating layer for insulating the first electrode is formed on the first electrode, and a first opening is provided in a part of this insulating layer. Subsequently, a second semiconductor circuit element is formed by forming a second electrode overlaying in part the insulating layer at an area other than the first opening and, a subsidiary conductive layer is formed in the first opening. Another insulating layer is formed on the structure thus formed, whereupon second and third openings are respectively provided in this latter insulating layer. First and second conductors are respectively deposited in the second and third openings, whereby electrical contact to the first and second electrodes are provided, with contact to the first electrode being via the subsidiary conductive layer.

Process for making a memory device

A semiconductor memory comprising a memory cell disposed on a p-type semiconductor substrate and including an insulated-gate field effect transistor and a storage capacitor. The storage capacitor comprises: an insulator capacitor including a first electrode disposed on the substrate, a film of Si.sub.3 N.sub.4 disposed on the first electrode, and a second electrode disposed on the Si.sub.3 N.sub.4 film; and a pn junction capacitor including a first n-type impurity region for constituting either the source or drain of the insulated-gate field effect transistor, and a second p-type impurity region disposed in contact with the first impurity region and having a higher impurity concentration than the substrate.

Semiconductor memory device

Semiconductor device and process for making the same

An enhancement-type and a depletion-type metal-insulator-semiconductor field effect transistor are formed on a common substrate of silicon and are electrically isolated from each other by a plurality of layers including, for example, a first layer of SiO.sub.2, a second layer of Al.sub.2 O.sub.3 capable of inducing holes in the surface portion of the substrate, and a third layer of SiO.sub.2, and the relation between the thicknesses of these layers is suitably selected for attaining the satisfactory isolation between these transistors.

MIS-FETs isolated on common substrate

In selectively etching a solid oxide thin film which has chemisorbed water (surface hydroxyl groups) in its surface, the thin film is surface-treated with an organic compound which has within its molecule a functional group to react with the surface hydroxyl groups. Thereafter, photo-etching is performed by the conventional method by applying a thin film of a photosensitive organic polymer onto the treated thin film. Through selection of the sort of the organic compound, the degree of side-etch arising in the process of the selective etch can be controlled.

Method for controlling the degree of side-etch in thin oxide films by

Growing community of inventors

Hachioji, Japan

Norikazu Hashimoto