Fuji Electric Co., Ltd.

Norihiro Komiyama

Yuichi Onozawa

Yuichi Harada

Yoshihiro Ikura

Seiji Noguchi

Masahiro Sasaki

Yosuke Sakurai

Shoji Yamada

Provided is a semiconductor device including: a semiconductor substrate having an upper surface and a lower surface and having a drift region of a first conductivity type; a first main terminal provided above the upper surface; a second main terminal provided below the lower surface; a control terminal configured to control whether or not to cause a current to flow between the first main terminal and the second main terminal; and a buffer region provided between the drift region and the lower surface and having a higher doping concentration than the drift region. In a C-V characteristic indicating a relationship between a power supply voltage applied between the first main terminal and the second main terminal and an inter-terminal capacitance between the control terminal and the second main terminal, a region where the power supply voltage is 500 V or more has a peak of the inter-terminal capacitance.

Semiconductor device

There is provided a semiconductor device including: a drift region of a first conductivity type disposed in a semiconductor substrate; a base region of a second conductivity type disposed above the drift region; an emitter region of the first conductivity type disposed above the base region; a plurality of trench portions arrayed in a predetermined array direction on a front surface side of the semiconductor substrate; a trench contact disposed on the front surface side of the semiconductor substrate between two adjacent trench portions; and a contact layer of the second conductivity type disposed under the trench contact and having a higher doping concentration than the base region, wherein a lower end of the trench contact is deeper than a lower end of the emitter region, and the emitter region and the contact layer are in contact with each other at a side wall of the trench contact.

Semiconductor device and fabrication method of semiconductor device having improved breaking withstand capability

Provided is a semiconductor device that has a plurality of gate trench portions electrically connected to a gate electrode, and a plurality of dummy trench portions electrically connected to an emitter electrode, and includes a first trench group that includes one gate trench portion and two dummy trench portions adjacent to the gate trench portion and adjacent to each other, and a second trench group that includes two gate trench portions adjacent to each other.

Provided is an analyzing apparatus including a charge amount analyzing unit configured to analyze, by using a device simulator configured to simulate a transient change of a charge in a semiconductor device having a first main terminal and a second main terminal, a change of a charge amount at any one of the terminals when a power source voltage applied between the first main terminal and the second main terminal is changed by a displacement voltage smaller than an initial voltage after a current flowing between the first main terminal and the second main terminal is stabilized with the semiconductor device being set to an ON state and the power source voltage being set to the initial voltage, and a capacitance calculating unit configured to compute a terminal capacitance at any one of the terminals based on the change of the charge amount analyzed by the charge amount analyzing unit.

Growing community of inventors

Matsumoto, Japan

Norihiro Komiyama