Texas Instruments Corporation

Noel M Russell

Stephan Grunow

Satyavolu Srinivas Papa Rao

Peijun Chen

Douglas E Mercer

Duofeng Yue

Anthony J Konecni

Montray Leavy

Doufeng Yue

Alwin J Tsao

Changming Jin

Richard Allen Faust

Kenneth Joseph Newton

Bobby D Strong

Christopher Lyle Borst

Li Chen

The present invention provides a method of manufacturing a metal silicide electrode () for a semiconductor device (). The method comprises depositing by physical vapor deposition, germanium atoms () and transition metal atoms () to form a metal-germanium alloy layer () on a semiconductor substrate (). The metal-germanium alloy layer and the semiconductor substrate are reacted to form a metal silicide electrode. Other aspects of the present invention include a method of manufacturing an integrated circuit ().

Metal-germanium physical vapor deposition for semiconductor device defect reduction

Devices and methods are presented to fabricate diffusion barrier layers on a substrate. Presently, barrier layers comprising a nitride layer and a pure metal layer are formed using a physical vapor deposition (PVD) process that requires multiple ignition steps, and results in nitride-layer thicknesses of no less than 2 nm. This invention discloses devices and process to produce nitride-layers of less than &#x3c;1 nm, while allowing for formation of a pure metal layer on the nitride-layer without re-igniting the plasma. To achieve this, the flow of nitrogen gas is cut off either before the plasma is ignited, or before the formation of a continuous-flow plasma. This ensures that a limited number of nitrogen atoms is deposited in conjunction with metal atoms on the substrate, thereby allowing for controlled thickness of the nitride layer.

Manufacturable reliable diffusion-barrier

The present invention provides a method for forming an interconnect on a semiconductor substrate. The method includes forming an openingover an inner surface of the opening, the depositing forming a reentrant profile near a top portion of the opening. A portion of barrieris etched, which removes at least a portion of the barrierto reduce the reentrant profile. The etching also removes at least a portion of the barrierlayer at the bottom of the opening

Contact resistance reduction by new barrier stack process

The present invention provides a method of manufacturing a metal silicide electrode () for a semiconductor device (). The method comprises depositing by physical vapor deposition, halogen atoms () and transition metal atoms () to form a halogen-containing metal layer () on a semiconductor substrate (). The halogen-containing metal layer and the semiconductor substrate are reacted to form a metal silicide electrode. Other aspects of the present invention include a method of manufacturing an integrated circuit () comprising the metal silicide electrode.

Metal-halogen physical vapor deposition for semiconductor device defect reduction

A method of fabricating a semiconductor device is provided. An interlayer dielectric layer is formed on one or more semiconductor layers (). One or more feature regions are formed in the interlayer dielectric layer (). A first conductive layer is formed in at least a portion of the feature regions and on the interlayer dielectric layer ()). A first anneal is performed that promotes grain growth of the first conductive layer (). An additional conductive layer is formed on the first conductive layer () and an additional anneal is performed () that promotes grain growth of the additional conductive layer and further promotes grain size growth of the first conductive layer. Additional conductive layers can be formed and annealed until a sufficient overburden amount has been obtained. Subsequently, a planarization process is performed that removes excess conductive material and thereby forms and isolates conductive features in the semiconductor device ().

Partial plate anneal plate process for deposition of conductive fill material

A method for fabricating a seed layer. A seed layer () is deposited over a barrier layer () using a three-step process comprising a low AC bias power step, a high AC bias power step, and a lower/zero AC bias power step. The low AC bias power step provides low overhang. The high AC bias power step provides good sidewall coverage. The lower/zero AC bias step recovers areas exposed by re-sputtering during the high AC bias power step.

Method of fabricating robust nucleation/seed layers for subsequent deposition/fill of metallization layers

A trench () is formed in a dielectric layer (). A first metal layer () is formed in the trench using physical vapor deposition. A second metal layer () is formed in the trench () over the first metal layer () using chemical vapor deposition. Copper () is used to fill the trench () by electroplating copper directly onto the second metal ().

Multilayer integrated circuit copper plateable barriers

A coil () is placed adjacent to a semiconductor wafer (). An AC excitation current is used to create a changing electromagnetic field () is the wafer (). The wafer is heated by a heat source () and the conductivity of the wafer () will change as a function of the wafer temperature. Induced eddy currents will cause the inductance of the coil () to change and the temperature of the wafer () can be determined by monitoring the inductance of the coil ().

Measurement of wafer temperature in semiconductor processing chambers

According to one embodiment of the invention, a method for forming multiple layers of a semiconductor device is provided. The method includes defining a via through a dielectric layer that overlies a first layer. The first layer comprises a conductive portion that at least partly underlies the via. The method also includes overfilling the via with a dielectric material to form a second layer that overlies the dielectric layer. The method also includes forming a trench that is connected to the via by etching through the second layer and the dielectric material in the via.

Methods for forming multiple damascene layers

A method ( ) of fabricating an electronic device ( ) formed on a semiconductor wafer. The method forms a dielectric layer ( ) in a fixed position relative to the wafer, where the dielectric layer comprises an atomic concentration of each of silicon, carbon, and oxygen. After the forming step, the method exposes ( ) the electronic device to a plasma such that the atomic concentration of carbon in a portion of the dielectric layer is increased and the atomic concentration of oxygen in a portion of the dielectric layer is decreased. After the exposing step, the method forms a barrier layer ( ) adjacent at least a portion of the dielectric layer.

Semiconductor device with silicon-carbon-oxygen dielectric having improved metal barrier adhesion and method of forming the device

Semiconductor devices and manufacturing methods therefor are disclosed, in which conductive fill structures are provided in fill regions in an interconnect wiring layer between conductive wiring structures to facilitate planarization uniformity during metalization processing. One approach employs fill structures of varying sizes where smaller fill structures are formed near wiring regions having high aspect ratio wiring structures and larger fill structures are located near wiring regions with lower aspect ratio wiring structures. Another approach provides fill structures with varying amounts of openings, with fill structures having few or no openings being provided near low aspect ratio wiring structures and fill structures having more openings being located near higher aspect ratio wiring structures.

Methods and semiconductor devices with wiring layer fill structures to improve planarization uniformity

A system for constructing semiconductor devices is disclosed. The system comprises a wafer (,) having semiconductor devices (,), a bevel (,), an edge (,), a frontside (,), and a backside (,). The system also has a chamber (,), and a heater (,) coupled to the interior of the chamber (,) and operable to hold and heat the wafer (,). A showerhead (,) is also coupled to the interior of the chamber (,) and is operable to introduce a precursor gas (,) containing copper over the wafer (,). A shield (,) is coupled to the interior of the chamber (,) and is operable to partially shield the bevel (,), the edge (,), and the backside (,) of the wafer (,) from the precursor gas (,). There is an opening (,) in the chamber (,) through which a reactive backside gas (,) may be introduced under the wafer (,). A method for constructing semiconductor devices is disclosed. Step one calls for placing a wafer (,) on a heater (,) in a chamber (,). Step two requires heating the wafer with a heater (,). Step three provides for partially shielding the wafer (,) with a shield (,). In step four, the method provides for introducing a precursor gas (,) containing copper into the chamber (,) above the wafer (,). The last step calls for introducing a reactive backside gas (,) into the chamber (,) below the wafer (,) through an opening (,).

Method and system for constructing semiconductor devices

A method for the chemical vapor deposition of titanium aluminum nitride layers. The method includes the steps of placing a substrate in a deposition reactor; introducing tetrakis-dimethyl-amido-titanium (TDMAT) into the reactor; and introducing dimethyl-aluminum-hydride (DMAH) into the reactor in the presence of the TDMAT. In one embodiment the TDMAT is introduced at a rate of between 10 and 1000 times the rate at which the DMAH is introduced. In another embodiment the substrate temperature is between about 200&deg; C. and 500&deg; C.

Method for forming titanium aluminum nitride layers

An embodiment of the instant invention is a method of fabricating a conductive structure for electrically connecting one portion of a semiconductor device to another portion of the device, the method comprising the steps of: providing a continuous liner layer (step 104) of the semiconductor substrate, the liner layer comprised of CVD Al; forming a first conductor (step 106) on the liner layer, the first conductor formed using a source whose output power is in the range of 1 to 5 kW; and forming a second conductor (step 108) on the first conductor, the second conductor formed using a source whose output power is in the range of 10 to 20 kW. Preferably, the conductive structure is selected from the group consisting of: contact, via, and trench. In an alternative embodiment, a nucleation layer is formed (step 104) beneath the continuous liner layer. The nucleation layer is, preferably, comprised of titanium or a Ti/TiN stack. Preferably, the step of forming a first conductor on the liner layer is comprised of depositing an aluminum containing layer using physical vapor deposition. In addition, the step of forming a second conductor on the first conductor is, preferably, comprised of depositing an aluminum containing layer using physical vapor deposition.

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Dallas, TX, United States of America

Noel M Russell