Tdk Corporation

Headway Technologies, Incorporated

Sae Magnetics (h.k.) Limited

Nobuyuki Okuzawa

Yoshitaka Sasaki

Hiroyuki Ito

Tatsuya Harada

Satoru Sueki

Makoto Yoshida

Tomokazu Ito

Hiroshi Ikejima

Junichiro Urabe

Kazuhiko Ito

Munehiro Takaku

Takashi Kudo

Yoshikazu Sato

Shota Suzuki

Makoto Otomo

Yukari Hishimura

Akira Furuya

Akira Sato

Toshiyuki Yoshizawa

Ryuji Hashimoto

Masahiro Miyazaki

Shirou Ootsuki

Wakiko Sato

Tadashige Konno

Masaomi Ishikura

Daisuke Hirose

Disclosed herein is a coil component that includes a resin body having a first resin-based insulating material and a second resin-based insulating material lower in relative permittivity than the first resin-based insulating material, a coil pattern embedded in the resin body and helically wound in a plurality of turns, and first and second terminal electrodes formed on a surface of the resin body and connected respectively to one and other ends of the coil pattern. The coil pattern has a part covered with the first resin-based insulating material and another part covered with the second resin-based insulating material.

Coil component

Disclosed herein is a coil component that includes a coil pattern embedded in an element body and helically wound in a plurality of turns. The element body includes a support body having a cavity formed therein and a first insulating layer stacked on the support body so as to cover the cavity, thereby forming a hollow space inside the element body. The coil pattern includes a plurality of first sections formed along an inner wall of the cavity and a plurality of second sections formed on the first insulating layer. One ends of the plurality of first sections are connected respectively to their corresponding one ends of the plurality of second sections. The other ends of the plurality of first sections are connected respectively to their corresponding other ends of the plurality of second sections.

Coil component and manufacturing method therefor

Disclosed herein is a coil component that includes a coil pattern embedded in a resin body. The resin body includes a winding core area surrounded by the coil pattern and having a first surface and a substantially flat second surface different in the circumferential direction position from the first surface, and a first surrounding area covering the first surface of the winding core area. The coil pattern includes first sections extending along the first surface of the winding core area and second sections extending along the second surface of the winding core area. One ends of the first sections are connected respectively to their corresponding one ends of the second sections. The other ends of the first sections are connected respectively to their corresponding other ends of the second sections.

A dielectric composition contains a complex oxide represented by a composition formula of BiZnNbO. x+y+z=1.00. x&#x3c;0.20. 0.20&#x2264;y&#x2264;0.50. 0.25&#x2264;x/z. A dielectric composition contains a complex oxide represented by a composition formula of BiZnNbO. x+y+z=1.00. 0.20&#x2264;y&#x2264;0.50. 1.5&#x3c;x/z&#x2264;3.0. z&#x3c;0.25.

Dielectric composition and electronic component

A dielectric composition including a complex oxide containing bismuth, zinc, and niobium, includes a crystal phase formed of the complex oxide and having a pyrochlore type crystal structure, and an amorphous phase. When the complex oxide is represented by a composition formula BiZnNbO, in which x, y, and z satisfy relations of x+y+z=1.00, 0.20&#x2264;y&#x2264;0.50, and 2/3&#x2264;x/z&#x2264;3/2.

A method of manufacturing a layered chip package that includes a main body, and wiring disposed on a side surface of the main body. The main body includes a plurality of layer portions. The method includes fabricating a plurality of substructures, and completing the layered chip package by fabricating the main body using the plurality of substructures and by forming the wiring on the main body. Each substructure is fabricated through the steps of: fabricating a pre-substructure wafer including a plurality of pre-semiconductor-chip portions aligned; distinguishing between a normally functioning pre-semiconductor-chip portion and a malfunctioning pre-semiconductor-chip portion among the plurality of pre-semiconductor-chip portions included in the pre-substructure wafer; and forming electrodes connected to the normally functioning pre-semiconductor-chip portion and having respective end faces located in the side surface of the main body on which the wiring is disposed, without forming any electrode connected to the malfunctioning pre-semiconductor-chip portion.

Method of manufacturing layered chip package

A layered chip package has a main body including pairs of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip. The pairs of layer portions include specific pairs of layer portions. Each of the specific pairs of layer portions includes a first-type layer portion and a second-type layer portion. The first-type layer portion includes electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the second-type layer portion does not include such electrodes. The specific pairs of layer portions are provided in an even number.

Layered chip package with wiring on the side surfaces

A layered chip package includes: a plurality of layer portions stacked, each of the layer portions including a semiconductor chip; and a heat sink. Each of the plurality of layer portions has a top surface, a bottom surface, and four side surfaces. The heat sink has at least one first portion, and a second portion coupled to the at least one first portion. The at least one first portion is adjacent to the top surface or the bottom surface of at least one of the layer portions. The second portion is adjacent to one of the side surfaces of each of at least two of the plurality of layer portions.

Layered chip package with heat sink

A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. The insulating portion has an end face located at the side surface of the main body on which the wiring is disposed. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the main body on which the wiring is disposed.

Layered chip package

The invention relates to a surface mount type electronic component mounted on a printed circuit board or hybrid IC (HIC) and a method of manufacturing the same and provides an electronic component which can be formed with a small size and a low height at a low cost and a method of manufacturing the same. A common mode choke coil as the electronic component has an overall shape in the form of rectangular parallelepiped that is provided by forming an insulation layer, a coil layer (not shown) formed with a coil conductor, and external electrodes electrically connected to the coil conductor in the order listed on a silicon substrate using thin film forming techniques. The external electrodes are formed to spread on a top surface (mounting surface) of the insulation layer.

Electronic component and method of manufacturing the same

A layered chip package has a main body including pairs of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip. The pairs of layer portions include at least one specific pair of layer portions including a first-type layer portion and a second-type layer portion. The first-type layer portion includes electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the second-type layer portion does not include such electrodes. A layered substructure formed of a stack of two substructures, each of which includes aligned preliminary layer portions, is used to fabricate a stack of a predetermined two or greater number of pairs of layer portions, and the main body is fabricated by stacking an additional first-type layer portion together with the stack, the number of the additional first-type layer portion being equal to the number of the specific pair(s) of layer portions included in the stack.

A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. The plurality of layer portions include at least one layer portion of a first type and at least one layer portion of a second type. The layer portions of the first and second types each include a semiconductor chip. The layer portion of the first type further includes a plurality of electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the layer portion of the second type does not include any electrode connected to the semiconductor chip and having an end face located at the side surface of the main body on which the wiring is disposed. The wiring is connected to the end face of each of the plurality of electrodes.

Layered chip package and method of manufacturing same

There is provided a method of manufacturing a coil component, where a first insulation layer is formed on a first magnetic substrate, an insulation film is formed on the first insulation layer, a coil conductor is formed on the insulation film, another insulation film is formed on the coil conductor, and an open region is formed on the inner circumference side and on the outer circumference side of the coil conductor. A magnetic later is embedded, at least partially, in the open region, and a second magnetic substrate is secured on the magnetic layer. Also, a plurality of electrode terminals are formed, where one of the electrode terminals is connected to a terminal portion of the coil conductor, and the electrode terminals are provided across sides of the first and second magnetic substrates. Therefore, the first insulation layer can suitably prevent shorting failures between the electrode terminals.

Method of manufacturing a coil component

A layered chip package includes a plurality of layer portions stacked, each layer portion including a semiconductor chip having a first surface with a device formed thereon and a second surface opposite thereto. The plurality of layer portions include at least a pair of layer portions disposed such that the first surfaces of the respective semiconductor chips face toward each other. A manufacturing method for the layered chip package includes the steps of: fabricating a layered substructure by stacking a plurality of substructures each including a plurality of layer portions corresponding to the plurality of layer portions of the layered chip package; and fabricating a plurality of layered chip packages by using the layered substructure. The step of fabricating the layered substructure includes: fabricating a first and a second pre-polishing substructure each having a first surface and a second surface; bonding the pre-polishing substructures to each other such that their respective first surfaces face toward each other; and forming a first and a second substructure by polishing the second surfaces.

Growing community of inventors

Tokyo, Japan

Nobuyuki Okuzawa