Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Ricoh Company, Ltd.

Taiyo Sanso Co., Ltd.

Nobuyoshi Hattori

Hideki Naruoka

Toshiaki Mugibayashi

Takaaki Fukumoto

Toshiaki Iwamatsu

Yasuo Yamaguchi

Takashi Ipposhi

Takuji Matsumoto

Shigeto Maegawa

Satoshi Yamakawa

Hidekazu Yamamoto

Junji Nakanishi

Tomio Iwasaki

Junji Kobayashi

Masahiro Sekine

Norio Ishitsuka

Hiroshi Kurokawa

Itaru Kanno

Naohiko Fujino

Masashi Ohmori

Yoko Miyazaki

Junko Izumitani

Masuo Tada

Masahiko Ikeno

Masaharu Hama

Motonori Yanagi

Osamu Wada

Isamu Karino

Kazuo Kuramoto

Tatsuya Aizawa

Kaoru Yamana

Fusami Soeda

Yoshitsugu Nakagawa

Koichiro Hori

Tomoki Tamada

An information processing deviceconfigured to transmit a file stored in a memory mediumto a terminal. The information processing device includes: a specifying information creating unitconfigured to create specifying information for specifying files stored in the memory medium, by using a file name and information about the memory medium; a transmitting unitconfigured to transmit the specifying information to the terminal; and a file transmitting unitconfigured to transmit to the terminal one of the files specified by the terminal in accordance with the specifying information.

Information processing device, imaging device, and system

After a gate electrode is formed on a main surface of a semiconductor substrate, low concentration layers are formed on the main surface of the semiconductor substrate by implanting impurities therein, with using the gate electrode as a mask. Thereafter, first sidewalls and second sidewalls are formed on the both side surfaces of the gate electrode. Subsequently, nitrogen or the like is ion-implanted into the semiconductor substrate, with using the first sidewalls, the second sidewalls and the gate electrode as a mask, thereby forming a crystallization-control region (CCR) on the main surface of the semiconductor substrate. Then, after the second sidewalls are removed, high concentration layers for a source and a drain are formed on the main surface of the semiconductor substrate.

Method of manufacturing a semiconductor device

A semiconductor device includes a semiconductor layer, a plurality of semiconductor elements formed on the semiconductor layer, and an isolation film provided in a surface of the semiconductor layer, semiconductor elements being electrically isolated from each other by the isolation film. The semiconductor device also includes a PN junction portion provided under the isolation film and formed by two semiconductor regions of different conductivity types in the semiconductor layer. The isolation film includes a nitride film provided in a position corresponding to a top of the PN junction portion and has a substantially uniform thickness across the two semiconductor regions and an upper oxide film and a lower oxide film which are provided in upper and lower portions of the nitride film. The surface of the semiconductor layer is silicidized in such a state that a surface of the isolation film is exposed.

Semiconductor device and method of manufacturing the same

A boat () has a recess () for supporting a laminated wafer (). The recess () has a first side surface (), a first bottom surface (), a second side surface (), a second bottom surface () and a third side surface (). Viewing from an upper surface of the boat (), the second bottom surface () is located in a position lower than the first bottom surface (). The laminated wafer () is mounted on the boat () in the state that a side surface of a first silicon wafer () is not in contact with the second bottom surface () of the recess () and a side surface of a second silicon wafer () is in contact with the first bottom surface () of the recess (). A second main surface () of the second silicon wafer () is in contact with the first side surface () of the recess () and a second main surface () of the first silicon wafer () is in contact with the third side surface () of the recess ().

Method of manufacturing SOI wafer

A computer-implemented method of process analysis allows for accurate analysis of the degree of achievement of a predetermined effect exhibited by a predetermined process included in a manufacturing operation. In a step S , a first manufacturing operation including a predetermined cleaning process is performed to form chips on wafers to be cleaned. In a step S , a second manufacturing operation including details identical to those of the first manufacturing operation except the predetermined cleaning process is performed to form chips on wafers not to be cleaned. In a step S , an electric tester is applied to all the chips formed on the wafers to be cleaned and the wafers not to be cleaned, to determine the quality of each chip. In a step S , all the chips are classified into four categories according to the kind of wafer (i.e., the wafer to be cleaned or the wafer not to be cleaned) and the quality as determined of each chip. Then, in a step S , the effect of improving the quality of a chip achieved by the predetermined cleaning process is analyzed using the classification performed in the step S as &ldquo;chip classification data&rdquo;.

Computer-implemented method of process analysis

In the step (S ), chip classification data in which a plurality of chips are classified into four sorts on the basis of presence/absence of (new) defects and pass/fail (of integrated circuits) is obtained. Next, in the step (S ) set is a situation where chips are randomly extracted out of all the chips with the number of chips with defect used as random extraction number on the basis of the chip classification data obtained in the step (S ). After that, in the step (S ) obtained is the random probability of failure (P(N4)) which is a probability that the number of faulty chips included in the randomly-extracted chips should be not less than the equivalent of the number (N4) of faulty chips with defect. Thus obtained is a defect analysis method and a method of verifying chip classification data, by which the analysis result on the basis of the chip classification data can be enhanced.

Computer-implemented method of defect analysis

A semiconductor device that prevents metal pollution and a method of manufacturing the semiconductor device. A region (NR) and a region (PR) are defined by a trench isolation oxide film, a polysilicon film selectively provided on the trench isolation oxide film, a silicon layer provided on the polysilicon film, and a side wall spacer provided on a side surface of the polysilicon film. The polysilicon film is provided in a position corresponding to a top of a PN junction portion JP of a P-type well region and an N-type well region in a SOI layer across the two well regions.

Semiconductor device

A defect analysis method makes it possible to quantitative grasp the influence of the number of new defects of a single process on the yield of a device. After the presence or absence of a new defect due to a specified process in each chip is judged, and defectiveness or non-defectiveness of the chip is judged by an electric tester, a plurality of chips on a wafer are classified into four groups: {circle around (1)} non-defective chip with no new defect; {circle around (2)} defective chip with no new defect; {circle around (3)} non-defective chip with new defect; and {circle around (4)} defective chip with new defect, to obtained the number of new defective chips considered to be caused only by the new defect of the specified process; a critical ratio of the new defect of the specified process, at which a chip is considered to become defective; and the number of process defective chips considered to be caused by the specified process.

Defect analysis method and process control method

First, a silicon germanium single-crystalline layer and a silicon single-crystalline layer are formed on a main surface of a bond wafer by epitaxy. The overall surface of the bond wafer is oxidized for forming a silicon oxide layer. Then, a base wafer is bonded to the bond wafer. The bond wafer and the base wafer bonded to each other are heated for reinforcing adhesion therebetween. Then, the bond wafer is removed by plasma etching with chlorine gas while making the silicon germanium single-crystalline layer serve as a stopper. Thereafter the silicon germanium single-crystalline layer is polished by chemical mechanical polishing to have a thickness suitable for forming a device. Thus implemented is a method of manufacturing an SOI substrate by bonding capable of employing a layer having a crystal state with small irregularity for serving as a stopper having selectivity for single-crystalline silicon and effectively using the stopper as a device forming layer.

SOI substrate and semiconductor device

Method of manufacturing SOI substrate and semiconductor device

A semiconductor device and a semiconductor storage device having an SOI structure and being enable sufficient gettering performance without imposing limitations on the freedom of design of an LSI circuit. A semiconductor device includes a semiconductor wafer of SOI structure which has a insulation layer and a silicon layer provided thereon, wherein the semiconductor wafer includes a plurality of element fabrication regions where semiconductor elements are fabricated, and a cutting region provided between the element fabrication regions. Gettering sites are formed in the cutting region by means of embedding a gettering member into grooves of predetermined depth.

Semiconductor device and semiconductor storage device

A quality management system (S,) comprises a data processing unit (,), a processed-data judgment unit (,) receiving an output from the data processing unit (,), a sampling unit (,) receiving an output from the processed-data judgment unit (,), a file making unit (,) receiving an output from the sampling unit (,), a data processing unit (,) receiving an output from an observation unit (,) and a processed-data judgment unit (,) receiving an output from the data processing unit (,). The system (S,) having this constitution allows reduction in labor and time from finding of a defect to recognition of occurrence of abnormal condition and improvement in accuracy of fatality rate of the defect.

Quality management system and recording medium

An ordinary user can easily learn a step at which a problem occurs during semiconductor manufacturing processes and improve the yield of manufacturing products and the quality of the products. At a certain in-line inspection step, a CPU (3) stores data signals (V1) taken by an inspection apparatus (1) into a memory (2), and reads a result (V6) obtained at a precedent step and stores the same in the memory (2). The CPU (3) reads stored data signals (V2) from the memory (2), performs comparison or referral on data about defects which are detected at a current step and the result (V6) regarding the precedent step, and generates a defect data analysis processing result signal (V5) regarding the current step. The result (V5) consists of disappeared defect data, common defect data, new defect data to which a label of a current step number is assigned, and reappeared defect data. The CPU (3) performs the processing above for each in-line inspection step, edits resultant data, and generates histogram data which provide the number of detected defects and the number of disappeared defects for each step.

Inspection data analyzing apparatus for in-line inspection with enhanced

Method for detecting and examining a slightly irregular surface state is provided which includes the steps of: illuminating a surface of a sample with light beam for detecting the slightly irregular surface state; observing a variation of the light beam occurring due to the slightly irregular surface state to specify the location of the slightly irregular surface state in an x-y plane of the sample; making the location of a probe needle of a scanning probe microscope and the location of the slightly irregular surface state on the sample coincide with each other; and measuring a three-dimensional image of the slightly irregular surface state by means of the scanning probe microscope. The scanning probe microscope for use in the aforementioned method and a method for fabricating a semiconductor device or a liquid crystal display device which utilizes the aforementioned method are also provided.

Method for detecting and examining slightly irregular surface states,

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Tokyo, Japan

Nobuyoshi Hattori