Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Nobutoshi Aoki

Takashi Izumida

Masaki Kondo

Toshiyuki Enda

Hiroyoshi Tanimoto

Tsukasa Nakai

Ichiro Mizushima

Takahisa Kanemura

Naoki Kusunoki

Fumitaka Arai

Riichiro Shirota

Koichi Kato

Hikari Tajima

Kazuya Ohuchi

Hideaki Aochi

Masaru Kito

Ryota Katsumata

Katsuyuki Sekine

Atsuhiro Kinoshita

Yoshinori Tsuchiya

Satoshi Inaba

Tsunehiro Ino

Akio Kaneko

Takashi Yamauchi

Junji Koga

Hiroki Tokuhira

Tatsufumi Hamada

Jyunichi Ozeki

Kimitoshi Okano

Takaya Yamanaka

Shinya Naito

Sanae Ito

Takayuki Kakegawa

Tomomi Kusaka

Takashi Kurusu

Jun Yamauchi

Hiroshi Watanabe

Masaru Kidoh

Makoto Mizukami

Daisuke Matsushita

Koichi Muraoka

Kiyotaka Miyano

Akihiro Nitayama

Tatsuya Ohguro

Yuichiro Mitani

Kouji Matsuo

Yasushi Nakasaki

Toshihiko Iinuma

Hiroshi Akahori

Takamitsu Ishihara

Masakazu Goto

Tadayoshi Uechi

Hirotaka Amakawa

Yuki Sekino

Tomomi Yoda

According to one embodiment, a semiconductor device includes a substrate; a stacked body provided on the substrate, the stacked body including a plurality of electrode layers stacked with an insulator interposed; a semiconductor body provided in the stacked body; and an insulating film. The semiconductor body includes a channel portion extending in a stacking direction of the stacked body, and a lower end portion of the semiconductor body provided between the channel portion and the substrate. The insulating film includes a charge storage film provided between the stacked body and the semiconductor body. A lower end portion of the insulating film surrounds the lower end portion of the semiconductor body. An upper surface of the lower end portion of the insulating film is provided at a lower height than an upper surface of the lower end portion of the semiconductor body in the stacking direction.

Method for manufacturing a semiconductor device including a vertical channel between stacked electrode layers and an insulating layer

Semiconductor device having vertical channel between stacked electrode layers and insulating layers

According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of conducting layers, a semiconductor layer, a variable resistive element, and a first wiring. The plurality of conducting layers are laminated in a first direction at predetermined pitches. The conducting layers extend in a second direction. The second direction is along the surface of the substrate. The semiconductor layer extends in the first direction. The variable resistive element is disposed at an intersection point between the plurality of conducting layers and the semiconductor layer. The first wiring is opposed to an inside of the semiconductor layer via a gate insulating film. The first wiring extends in the first direction. The semiconductor layer at least includes a first part and a second part. The first part is upward of the conducting layer on a lowermost layer. The second part is downward of the first part. The first part has a first length in a third direction. The third direction is intersecting the first direction and the second direction, and is along the surface of the substrate. The second part has a second length in the third direction. The second length is shorter than the first length.

Nonvolatile semiconductor memory device

A non-volatile memory device includes a first electrode layer, a second electrode layer adjacent to the first electrode layer, a third electrode layer adjacent to the second electrode layer, a fourth electrode layer adjacent to the third electrode layer, and a channel body extending through the first electrode layer, the second electrode layer, the third electrode layer and the fourth electrode layer in a first direction. The device further includes a circuit electrically connected to the first electrode layer, the second electrode layer, the third electrode layer, the fourth electrode layer, and the channel body. The circuit providing the second electrode layer with a first potential, the third electrode layer with a second potential higher than the first potential, the fourth electrode layer with a third potential between the first potential and the second potential and the channel body with a potential rising in the first direction.

Non-volatile memory device and method for reading out data

An integrated circuit device according to an embodiment includes a semiconductor substrate, a first semiconductor member and a second semiconductor member provided on the semiconductor substrate, a first electrode disposed between the first semiconductor member and the second semiconductor member, and a second electrode disposed between the semiconductor substrate and the first electrode. The first semiconductor member and the second semiconductor member extend in a first direction perpendicular to an upper surface of the semiconductor substrate. The first semiconductor member and the second semiconductor member are separated in a second direction orthogonal to the first direction. The first electrode extends in a third direction intersecting both the first direction and the second direction. The second electrode extends in the third direction.

Integrated circuit device

According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell which stores data with two or more levels. The memory cell includes a structure includes a first electrode layer, a first semiconductor layer, a phase change film, an electrical insulating layer, a second semiconductor layer, and a second electrode layer arranged in order thereof, and the first semiconductor layer and the second semiconductor layer have carrier polarities different from each other.

According to one embodiment, a nonvolatile semiconductor memory device comprises memory cells each which stores data with two or more levels. Each of the memory cells includes a semiconductor layer, a first insulating layer on the semiconductor layer, a charge storage layer on the first insulating layer, a second insulating layer on the charge storage layer, and a control gate electrode on the second insulating layer, and the second insulating layer includes a ferroelectric layer.

According to one embodiment, a nonvolatile semiconductor memory device comprises a semiconductor substrate, and a memory cell which is arranged on the semiconductor substrate and comprises a variable resistance element. The variable resistance element comprises a laminated structure including a phase-change element which has at least two different crystalline resistance states by varying a crystalline state, and a magnetoresistive element which has at least two different magnetization resistance states by varying a magnetization state, and applies or does not apply a magnetic field to the phase-change element in accordance with the magnetization state.

Nonvolatile semiconductor memory device and operating method of the same

According to one embodiment, a magnetoresistive element includes a first magnetic layer, a second magnetic layer, a non-magnetic layer formed between the first magnetic layer and the second magnetic layer, a charge storage layer having a first surface and a second surface different from the first surface, the first surface facing the second magnetic layer, a first insulating layer formed between the second magnetic layer and the first surface of the charge storage layer, and a second insulating layer formed on the second surface of the charge storage layer.

Magnetoresistive element and writing method of magnetic memory

According to one embodiment, a semiconductor storage device includes a first insulating film formed on a substrate and functioning as a FN (Fowler-Nordheim) tunnel film, a first floating gate formed on the first insulating film, an inter-floating-gate insulating layer formed on the first floating gate and functioning as a FN tunnel film, a second floating gate formed on the inter-floating-gate insulating layer, a second insulating film formed on the second floating gate, and a control gate formed on the second insulating film. The inter-floating-gate insulating layer includes a third insulating film and a fourth insulating film having a charge trap property which are stacked.

Semiconductor storage device and method for manufacturing the same

According to an aspect of the present invention, there is provided a semiconductor memory device including: a semiconductor substrate having: a contact region; a select gate region; and a memory cell region; a first element isolation region formed in the contact region and having a first depth; a second element isolation region formed in the select gate region and having a second depth; and a third element isolation region formed in the memory cell region and having a third depth which is smaller than the first depth.

Semiconductor memory device

According to one embodiment, there is provided a nonvolatile semiconductor memory device including a substrate, a laminated film which has a configuration where first insulating layers and first electrode layers are alternately laminated in a first direction vertical to the substrate, a second insulating layer formed on an inner wall of a first through hole pierced in the first insulating layers and the first electrode layers along the first direction, an intermediate layer formed on a surface of the second insulating layer, a third insulating layer formed on a surface of the intermediate layer, and a pillar-like first semiconductor region which is formed on a surface of the third insulating layer and extends along the first direction.

According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a floating gate electrode formed on the gate insulating film, made of polysilicon containing a p-type impurity as a group XIII element, and having a lower film and an upper film stacked on the lower film, an inter-electrode insulating film formed on the floating gate electrode, and a control gate electrode formed on the inter-electrode insulating film. One of a concentration and an activation concentration of the p-type impurity in the upper film is higher than one of a concentration and an activation concentration of the p-type impurity in the lower film.

Nonvolatile semiconductor memory device and method of manufacturing the same

According to one embodiment, a semiconductor device includes an element region partitioned by an isolation region in a semiconductor substrate, and a source region and a drain region formed in a surface layer of the element region by being isolated by a gate trench along a predetermined direction across the element region. The semiconductor device includes a gate electrode formed to reach a position deeper than the source region and the drain region by embedding at least part thereof in the gate trench with a gate dielectric film interposed therebetween. An interface in the drain region, which is in contact with the gate dielectric film, includes a projection projecting toward the gate electrode side.

Semiconductor device and manufacturing method thereof

According to one embodiment, a nonvolatile semiconductor memory includes control gates provided in an array form, the control gates passing through the first semiconductor layer, data recording layers between the first semiconductor layer and the control gates, two first conductive-type diffusion layers at two ends in the first direction of the first semiconductor layer, two second conductive-type diffusion layers at two ends in the second direction of the first semiconductor layer, select gate lines extending in the first direction on the first semiconductor layer, and word lines extending in the second direction on the select gate lines. The select gate lines function as select gates shared by select transistors connected between the control gates and the word lines arranged in the first direction. Each of the word lines is commonly connected to the control gates arranged in the second direction.

Nonvolatile semiconductor memory

Growing community of inventors

Yokohama, Japan

Nobutoshi Aoki