Renesas Technology Corp.

Nobutaka Imanishi

Yutaka Takikawa

Koichi Kawauchi

Kazuo Nomura

Kazuyuki Kawamoto

Satoko Kamakura

A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gates, two rows' worth of floating gates are arranged. The plurality of floating gates are placed in a staggered arrangement (in other words, in a zigzag pattern). That is, looking at one floating gate in a specific column and another floating gate in a column adjacent to that specific column, those floating gates deviate from each other in the Y direction.

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Hyogo, Japan

Nobutaka Imanishi