Hitachi, Ltd.

Renesas Technology Corp.

Nobuo Tanba

Hideaki Uchida

Shinji Nakazato

Takahide Ikeda

Kiyoo Itoh

Takao Watanabe

Yutaka Kobayashi

Ryoichi Hori

Goro Kitsukawa

Katsuhiro Shimohigashi

Noriyuki Homma

Masahiro Yamamura

Yoshikazu Saito

Atsushi Hiraishi

Kazunori Onozawa

Nobuyuki Gotoo

Yoshikasu Saito

Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.

Semiconductor memory device

Semiconductor memory device having separately biased wells for isolation

Semiconductor CMOS memory device with separately biased wells

Semiconductor memory device having bipolar transistor and structure to

A semiconductor device facilitates keeping all parasitic resistance values between contact portion of a common source (V.sub.cc) line and intrinsic collector operation regions of respective transistors small enough so as not to exceed predetermined values and so as to be nearly identical. The parasitic resistance values are made small and nearly identical by disposing collector electrode connecting layers between base impurity introducing layers of respective transistors provided with predetermined intervals in a semiconductor substrate. Because of this arrangement to minimize and equalize resistances, the voltage drops generated by the parasitic resistances applied to respective transistors are suppressed so as to be lower than or not substantially exceed the operation threshold voltages of the parasitic transistors.

Semiconductor device

Disclosed is here a semicondutor integrated circuit device and a method of manufacturing the same in which bipolar transistors and MISFETs are formed on a semiconductor substrate. Emitter and base electrodes of the bipolar transistors and gate, source, and drain electrodes of the MISFETs are constituted with the same polycrystalline layer, thereby realizing a high integration and a high-speed operation of a Bi-CMOS device.

Method of manufacturing a semiconductor device utilizing a single

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Palo, CA, United States of America

Nobuo Tanba