Hitachi, Ltd.

Renesas Technology Corp.

Hitachi Vlsi Engineering Corp.

Other

Hitachi-kokusai Electric Inc.

Renesas Electronics Corporation

Hitachi Ulsi Engineering Corp.

Nobuo Owada

Junji Noguchi

Hizuru Yamaguchi

Naofumi Ohashi

Mitsuaki Horiuchi

Jun Sugiura

Osamu Kasahara

Masatoshi Tsuneoka

Hiroyuki Akimori

Hideo Aoki

Isamu Asano

Tsuyoshi Tamaru

Yoshinao Kawasaki

Masakazu Sagawa

Osamu Tsuchiya

Tatsuyuki Saito

Toru Kaga

Fumio Ootsuka

Kazuyoshi Torii

Hiromichi Enami

Hidetsugu Ogishi

Makoto Ogasawara

Keisuke Funatsu

Takayoshi Kogano

Seiichirou Shirai

Atsushi Wakahara

Sinichi Suzuki

Nobuhiro Otsuka

Yoshihiro Ikeda

Tomotsugu Shimmyo

Tunehiko Tubone

Ken Tsugane

Yoshio Homma

Seiichi Kondo

Toshinori Imai

Kenichi Takeda

Kenji Hinode

Hizuru Yamaguchii

Tohru Kobayashi

Mikinori Kawaji

Noriyuki Sakuma

Kaoru Oogaya

Hizuru Uda

Hiroyuki Ohta

Akihiro Yaguchi

Atsuo Watanabe

Sueo Kawai

Norio Ishitsuka

Shigeki Hirasawa

Kazushige Sato

Kenichi Kikushima

Masaya Iida

Yuichi Wada

Shunji Sasabe

Takahisa Nitta

Takahiro Maeda

Takeshi Taniguchi

Atsumi Aoki

Sekiko Ozono

Atsumi Yasuda

Tadayuki Taneoka

Tadashi Kamata

Mitsuharu Honda

A method for manufacturing a semiconductor device includes the steps of: loading a substrate into a reaction chamber; supplying reactive gases into the reaction chamber and processing the substrate; and unloading the processed substrate from the reaction chamber, wherein the step of processing the substrate includes: a first film formation step of setting the substrate to a first temperature and forming a first silicon film including impurity atoms on the substrate and a second film formation step of setting the substrate to a second temperature, which is lower than the first temperature, and forming a second silicon film that includes no impurity atoms or has an impurity concentration lower than that of the first silicon film on at least the first silicon film.

Method for manufacturing semiconductor device, and substrate processing apparatus

A semiconductor IC device includes a buried interconnection in interconnection layers over a semiconductor substrate, in which electrical connection of interconnections are provided over and under an interconnection layer of an embedded interconnection from among the interconnection layers such that a first connecting conductor portion within a connecting hole extending from an upper interconnection toward the interconnection layer of a predetermined buried interconnection and a second connecting conductor portion within the connecting hole extending from a lower interconnection toward the interconnection layer of the predetermined buried interconnection are electrically connected via a connecting conductor portion for relay in the connecting groove of the interconnection layer of a predetermined buried interconnection. The connecting conductor portion for relay is sized so that the length of the connecting conductor portion for relay in an extending direction of the predetermined buried interconnection is longer than that of the connecting hole.

Semiconductor integrated circuit device and fabrication process thereof

In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.

Process for manufacturing semiconductor integrated circuit device

A manufacturing method of a semiconductor device includes the steps of carrying a substrate in a processing chamber, bringing the processing chamber into a state at a first pressure by supplying a silicon compound gas which contains carbon and hydrogen into the processing chamber, forming a silicon oxide film on the substrate by irradiating a UV light to the silicon compound gas supplied into the processing chamber in the state kept at the first pressure, and decompression process to bring the processing chamber into a state at a second pressure lower than the first pressure. This makes it possible to form the dense silicon oxide film in the trench with high aspect ratio and small width.

Manufacturing method of semiconductor device

In a fabrication process of a semiconductor integrated circuit device, upon effecting connection of an interconnection made of aluminum or aluminum alloy and another interconnection made of Cu or Cu alloy, a barrier conductor film or plug is disposed at the joint portion between these interconnections. Among the interconnection layers formed, the uppermost one is made of a wiring material such as aluminum or aluminum alloy, while the lower one is made of Cu or Cu alloy. The lowest interconnection is made of a conductive material other than Cu or Cu alloy. For example, the conductive material which permits minute processing and has both low resistance and high EM resistance such as tungsten is employed.

Fabrication process for a semiconductor integrated circuit device

Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.

Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same

After formation of Cu interconnectionstoeach to be embedded in an interconnection grooveof a silicon oxide filmby CMP and then washing, the surface of each of the silicon oxide filmand Cu interconnectionstois treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.

Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device

In a semiconductor integrated circuit device, upon connection of an interconnection made of aluminum or aluminum alloy and another interconnection made of Cu or Cu alloy, a barrier conductor film or plug is disposed at the joint portion between these interconnections. Among the interconnection layers, the uppermost one is made of a wiring material such as aluminum or aluminum alloy, while the lower, one is made of Cu or Cu alloy. The lowest interconnection is made of a conductive material other than Cu or Cu alloy. For example, the conductive material which permits minute processing and has both low resistance and high EM resistance such as tungsten is employed.

A semiconductor device comprises a semiconductor substrate; a first insulating film overlying a surface of the semiconductor substrate, an upper surface of the first insulating film being nitrided; a first copper-embedded interconnection embedded in the first insulating film, and which first copper-embedded interconnection contains copper as a main component; a copper nitride film overlying an upper surface of the first copper-embedded interconnection; a cap insulating film overlying an upper surface of the first insulating film and an upper surface of the copper nitride film; and a second insulting film overlying the cap insulating film.

After formation of Cu interconnections to each to be embedded in an interconnection groove of a silicon oxide film by CMP and then washing, the surface of each of the silicon oxide film and Cu interconnections to is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.

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Ome, Japan

Nobuo Owada