Kabushiki Kaisha Toshiba

Nobuaki Otsuka

Osamu Hirabayashi

Shigeru Atsumi

Hironori Banba

Masao Kuriyama

Seiichi Mori

Tomoaki Yabe

Takahiko Sasaki

Keiichi Kushida

Seiji Yamada

Yasushi Kameda

Shuso Fujii

Tooru Tanzawa

Shinji Saito

Sumio Tanaka

Akira Umezawa

Tadashi Miyakawa

Akira Katayama

Gou Fukano

Naoto Tomita

Yukinori Uchino

Yasuhisa Takeyama

Hiroshi Hatada

A fuse link is formed between first and second terminals. The first and second terminals and fuse link have a polysilicon layer and a layer formed on the polysilicon layer and containing a metal element. At least a portion of the fuse link is an amorphous silicon layer.

Semiconductor electrically programmable fuse element with amorphous silicon layer after programming and method of programming the same

A semiconductor memory device includes a first inverter ad a second inverter, a first power supply control circuit, and a second power supply control circuit. The first and second inverters constitute a memory cell and each have an input terminal and an output terminal connected crosswise to an output terminal and an input terminal, respectively, of the other. The first power supply control circuit supplies a first voltage to the first inverter. The second power supply control circuit supplies a second voltage to the second inverter. The first and second power supply control circuits control the first and second voltages, respectively, supplied to the first and second inverters in a selected memory cell for a writing operation in accordance with write data.

Semiconductor memory device with improved resistance to disturbance and improved writing characteristic

A level shifter circuit converts a signal generated by an internal circuit which operates with a first power supply, into a signal by a second power supply having voltage higher than that of the first power supply. The voltages at substrate terminals of two NMOS transistors, to which complementary two signals by the first power supply are input, is boosted to voltage higher than circuit ground potential in a period in which a voltage level of one of the two input signals and a voltage level of an output signal by the second power supply do not coincide with each other.

Level shifter circuit

A semiconductor memory device includes a first block and a second block adjacent to each other in a column direction, each block including first and second memory cell arrays each including a plurality of local bit lines and a local sense amplifier shared by the first and second memory cell arrays, a plurality of global bit lines shared by the first block and the second block, a global sense amplifier configured to sense data transferred to the global bit lines, first and second replica cell groups provided in the first and second blocks, first and second replica bit lines connected to the first and second replica cell groups, an activation circuit connected to each replica bit line, and configured to activate the local sense amplifier, an edge cell group surrounding the first block and the second block, and a contact region surrounding the edge cell group.

Semiconductor memory device including a static memory cell

This semiconductor memory device comprises a plurality of sub-arrays with a plurality of memory cells arranged in matrix form. Each local bit line is connected to a plurality of memory cells that are arranged in column direction in the sub-arrays. In addition, a global bit line is connected to the plural local bit lines. A column decoder is connected to the global bit line. The global bit line extends from the column decoder toward the plurality of sub-arrays, and it is cut before the furthest sub-array formed in the furthest region from that column decoder.

Semiconductor memory device

A semiconductor memory device includes a memory cell array provided in a cell array area and including a plurality of memory cells, a source potential line which applies a source potential to the memory cells, a switching element group provided in the cell array area adjacent to the memory cell array, the switching element group electrically connecting the source potential line to a ground potential line, when the memory cells are in an operation mode, a first P-type MIS transistor connected between the source potential line and the ground potential line, and fixing the source potential when the memory cells are in the sleep mode, and a bias generation circuit provided in a peripheral circuit area, and supplying a first bias potential to the first MIS transistor, the first MIS transistor being provided in the peripheral circuit area.

A semiconductor memory device includes a first inverter circuit and a second inverter circuit, a first transfer gate which is connected between a first power node of the first inverter circuit and a first bit line, a second transfer gate which is connected between a second power node of the second inverter circuit and a second bit line, a first word line connected to gate terminals of the first transfer gate and the second transfer gate, a first read transistor connected between the first power node and a second word line, a second read transistor connected between the second power node and the second word line, and an application circuit which is connected to the second word line, and applies a read voltage to the second word line in reading data.

Disclosed is an SRAM including a latch circuit, first and second write transfer gates, first and second write buffer transistors, read driver transistor, and read transfer gate. A write path is formed by connecting first and second write transfer gates and first and second write buffer transistors to the latch circuit which stores data and the path is controlled by use of a word line and data write bit lines. Further, a read path is formed by connecting a read driver transistor and read transfer gate to the latch circuit and the path is controlled by use of the word line, read bit line and data of the latch circuit.

Memory cell structure of SRAM

A flip-flop includes a first storage node at one terminal and a second storage node at the other terminal. The gate of a first MOS connects to the first storage node. The gate of a second MOS connects to the second storage node. One end of the current path of a first transfer connects to one end of the current path of the first MOS. One end of the current path of a second transfer connects to one end of the current path of the second MOS. The anode of a first diode connects to the first storage node. The cathode of the first diode connects to one end of the current path of the second transfer. The anode of a second diode connects to the second storage node. The cathode of the second diode connects to one end of the current path of the first transfer.

Semiconductor memory device and semiconductor device

A semiconductor device includes a first nonvolatile memory element group which includes a plurality of first nonvolatile memory elements programmed with data by electrically and irreversibly varying device characteristics, a verify circuit which detects a defective first nonvolatile memory element in the first nonvolatile memory element group, and a second nonvolatile memory element group which includes a plurality of second nonvolatile memory elements programmed with data by electrically and irreversibly varying device characteristics and which stores address data to rescue the defective first nonvolatile memory element.

Nonvolatile memory including a verify circuit

A semiconductor device includes a first fuse circuit group and a plurality of second fuse circuit groups. The first fuse circuit group, in which n-bit data is written, is electrically programmable. Each of the plurality of second fuse circuit groups has a first storage unit which is electrically programmable and stores m-bit (m is an integral submultiple of n) rewrite data, and a second storage unit which stores the address of a bit to be written in the first fuse circuit group.

Semiconductor device having storage circuit which stores data in nonvolatile manner by using fuse element

One fuse set is constituted of a plurality of fuse blocks. Each of the blocks includes a sub-fuse set constituted of fuse elements electrically programmable, and a program control circuit which controls programming of the fuse elements. One of the fuse elements is an enable bit representing validity/invalidity of the sub-fuse set. One fuse block becoming an object of the programming is determined in accordance with a value of the enable bit.

Fuse circuit

A resistance division circuit disclosed herein has a first MIS transistor having a first gate terminal, a first source terminal, a first drain terminal and a first back gate terminal, wherein the first gate terminal is regarded as a first terminal, and the first source terminal, the first drain terminal and the first back gate terminal are regarded as a second terminal, and one of the first terminal and the second terminal is connected to a first node of a first voltage; and a second MIS transistor having a second gate terminal, a second source terminal, a second drain terminal and a second back gate terminal, wherein the second gate terminal is regarded as a third terminal, and the second source terminal, the second drain terminal and the second back gate terminal are regarded as a fourth terminal, and one of the third terminal and the fourth terminal is connected to the other of the first terminal and the second terminal and the other of the third terminal and the fourth terminal is connected to a second node of a second voltage.

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Komae, Japan

Nobuaki Otsuka