Infineon Technologies LLC

Nobuaki Hata

Clifford Alan Zitlaw

Yuichi Ise

Stephan Rosner

A method can include, in a default mode of a memory device, decoding command data received on a unidirectional command address (CA) bus of a memory interface according to a first standard. In response to decoding a mode enter command, placing the memory device into an alternate management mode. In the alternate management mode, receiving alternate command data on the CA bus, and in response to receiving a command execute indication on the CA bus, decoding alternate command data according to a second standard to execute an alternate command. In response to decoding a mode exit command received on the CA bus according to the first standard, returning the memory device to the default mode. The memory interface comprises the CA bus and a data bus, and the CA bus and data bus comprise a plurality of parallel input connections. Corresponding devices and systems are also disclosed.

Methods, devices and systems for including alternate memory access operations over memory interface

In an embodiment, a method includes: receiving, via control lines of a parallel interface of a memory device, a first command and a first read command including one or more bits indicative of a first selection that causes a selector circuit to select data from a data memory portion of the memory device; providing, via data lines of the parallel interface, first data from the data memory portion using the selector circuit, where the provided first data is associated with the first read command; receiving, via the control lines, a second command and a second read command including one or more bits indicative of a second selection that causes the selector circuit to select data from an ECC memory portion; and providing, via the data lines, first ECC values from the ECC memory portion using the selector circuit, where the first ECC values are associated with the first data.

Growing community of inventors

Tokyo, Japan

Nobuaki Hata