Adv Antest Corporation

Noboru Okino

Kenichi Fujisaki

Makoto Tabata

Hiromi Oshima

Yasuhiro Kawata

Masumi Okino, Legal Representative

There is provided a testing apparatus including a plurality of test units, a storage that is shared by the plurality of test units, where the storage stores therein wafers under test to be tested by the plurality of test units, a transport mechanism that transports the wafers under test between the storage and each of the plurality of test units, a mainframe that specifies a test procedure for each of the plurality of test units, a power source that is shared by the plurality of test units, where the power source supplies power to each of the plurality of test units, and a pressure source that is shared by the plurality of test units, where the pressure source supplies a pressure to each of the plurality of test units. Here, each of the plurality of test units includes a test module that transmits and receives a test signal to/from a plurality of circuits formed on a wafer under test, a connector that connects together transmission paths of the test signal between the test module and the wafer under test, a holding member that brings the wafer under test into contact with the connector when supplied with the pressure, and a housing that houses therein the holding member and the connector, where the wafer under test is to be tested within the housing.

Testing apparatus

A memory testing method and apparatus are provided, which can test in short time a flash memory. In case of testing a flash memory having block function, in a memory testing method and apparatus in which a predetermined logical value is written in memory cells constituting each of blocks of the memory, the written logical value is read out from the memory cells to compare it with an expected value, and a decision that, when the read-out logical value and the expected value do not coincide with each other, such memory cell is a failure memory cell, a decision is rendered that, when the number of failure memory cells in each block reaches a predetermined number, such block is a bad block, and the test of such block is stopped. In addition, a decision is rendered that, when the number of failure memory cells on the same address line reaches a predetermined number, such address line is a bad address line, and after such decision has rendered, the test of memory cells on the bad address line is substantially not effected.

Memory testing method and memory testing apparatus

A memory block is subject to an erasure operation by a batch operation. Subsequently, a read-out test is conducted upon the memory block to count the number of unerased memory cells. If the count F is equal to or greater than a given number T , a plurality of erasure operations are conducted consecutively next. If F <T , a single erasure operation is conducted next, subsequently followed by a read-out test. The erasure operations and the read-out tests are repeated.

Semiconductor memory testing method and apparatus

A failure analysis of a semiconductor memory compares data written into and out of each cell of the semiconductor memory. When there is a disagreement, a '1' is written into a failure analysis memory. A disagreement signal is applied as a write command to column and row address fail count memories and is counted by a fail counter. The column address and row address fail count memories receive the column and row addresses, respectively. When the write command is applied to the column and row address fail count memories, the number of defective cells is read out of the memory addresses by a read modify write operation. A 1 is added by column and row adders to the number of defective cells read out, and the results are written into the column and row address fail count memories. The number of defective cells is read out of the column address fail count memory and compared with a number of row spare lines of the memory under test. When the former is greater than the latter, the column address is decided as a failing address line, is counted by a failing address line counter and is written into a failing address memory. The row address is sequentially changed, beginning with a 0, at each failing column address when a '1' is read out of the failure analysis memory. The contents of the memories are each rewritten by subtracting a 1 therefrom and the fail counter is decremented by one.

Analyzing device for saving semiconductor memory failures

A logic circuit part, which is composed of a flip-flop group and a combinational circuit and performs a sequential logic operation, is added with a specify circuit for selectively specifying desired flip-flop circuits in the flip-flop group and a write circuit for applying a set or reset signal to the flip-flop circuits selectively specified by the specify circuit. Each flip-flop circuit includes: a flip-flop for writing input data in response to a system clock; a first AND gate which, when the flip-flop circuit is selectively specified by the specify circuit, passes therethrough the set signal to set the flip-flop; a second AND gate which, when the flip-flop circuit is selectively specified by the specify circuit, passes therethrough the reset signal to reset the flip-flop; and a third and gate which, when the flip-flop circuit is selectively specified by the specify circuit, passes therethrough the output logic of the flip-flop to the outside.

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Tokyo, Japan

Noboru Okino