Applied Materials, Inc.

Micro Materials Inc.

Asml Us, Inc.

Applied Material, Inc.

Applied Mateials, Inc.

Mirocmaterials LLC

Appled Materials, Inc.

Nitin K Ingle

Anchuan Wang

Shankar Venkataraman

Xikun Wang

Abhijit Basu Mallick

Zhijun Chen

Jingchun Zhang

Zihui Li

Dmitry Lubomirsky

Ching-Mei Hsu

Jiayin Huang

Mikhail Korolik

Jingmei Liang

Jie Liu

Randhir P Thakur

Zheng Yuan

Soonam Park

Xinglong Chen

Vinod Robert Purayath

Young Seen Lee

Seung H Park

Jing Tang

Hiroshi Hamana

Jeffrey W Anthis

Dongqing Yang

Zhenjiang Cui

Robert Jan Visser

Regina Germanie Freed

Ho-yung David Hwang

Uday Mitra

Mandar Balasaheb Pandit

Ying Di Zhang

Benjamin Schmiege

Lin Xu

Edwin C Suarez

Fei C Wang

Jang-Gyoo Yang

Tom K Choi

Vikash Banthia

Srinivas D Nemani

Prerna Sonthalia Goradia

Bo Qi

Xiaolin C Chen

Jungmin Ko

Qiwei Liang

Susmit Singha Roy

Jay D Pinson, Ii

Adib M Khan

Geetika Bajaj

David Benjaminson

Ludovic Godet

Mei Yin Chang

Ellie Y Yieh

Karthik Janakiraman

He Ren

Xinliang Lu

Rui Cheng

Saurabh Garg

Gaurav Thareja

Chien-Teh Kao

Roey Shaviv

Suketu Arun Parikh

Sanjay S Natarajan

Jianxin Lei

Zhenbin Ge

Tomohiko Kitajima

Ming Xia

Won B Bang

Jonghoon Baek

Yen-Kun Victor Wang

DongQing Li

Sung-Kwan Kang

Chang Seok Kang

Tien Fak Tan

David P Thompson

Steven Verhaverbeke

Timothy Weidman

Pravin K Narwankar

Reza Arghavani

Rong Pan

Abhishek Dube

Roman Gouk

Sang-Jin Kim

Huixiong Dai

Naomi Yoshida

Martin Jay Seamons

Ralf Hofmann

Yi Zheng

Matthew L Miller

Joung Joo Lee

Toan Q Tran

Takehito Koshizawa

Christopher L Beaudry

Jun Xue

Gill Yong Lee

Cara Beasley

David Knapp

Nicolay Kovarsky

Paul L Deaton

Timothy B Michaelson

Exemplary methods for a coating a component of a semiconductor processing system may include forming a nickel-containing alloy on an exposed surface the component of the semiconductor processing system. The methods may include forming plasma effluents of a fluorine-containing precursor. The methods may include contacting the nickel-containing alloy with the plasma effluents of the fluorine-containing precursor. The contacting may fluorinate a portion of the nickel-containing alloy to form a nickel-and-fluorine-containing material overlying the nickel-containing alloy.

Semiconductor chamber components with advanced dual layer nickel-containing coatings

Exemplary semiconductor processing methods may include providing an oxygen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. A first layer of silicon-and-germanium-containing material, a second layer of silicon-and-germanium-containing material, and a layer of silicon-containing material may be disposed on the substrate. The methods may include contacting the substrate with the oxygen-containing precursor. The contacting may oxidize at least a portion of the second layer of silicon-and-germanium-containing material. The methods may include providing a first etchant precursor to the processing region and contacting the substrate with the first etchant precursor. The contacting may selectively etch the first layer of silicon-and-germanium-containing material. The methods may include providing a second etchant precursor to the processing region. The methods may include contacting the substrate with the second etchant precursor. The contacting may etch a portion of the layer of silicon-containing material.

Selective etching of silicon-and-germanium-containing materials with increased surface purities

Exemplary methods of semiconductor processing include delivering a carbon-containing precursor and a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. A flowrate ratio of the hydrogen-containing precursor to the carbon-containing precursor may be maintained greater than or about 2:1. The methods include forming a layer of graphene on a substrate positioned within the processing region of the semiconductor processing chamber. The substrate may be maintained at a temperature below or about 600° C.

Low temperature graphene growth

A substrate processing method includes creating a mask on a top surface of a workpiece. A first portion of a gap fill material is overlaid by the mask and a second portion of the gap fill material is exposed through an opening in the mask. The method further includes exposing the workpiece to a plasma. The method further includes performing a first etching of the first portion of the gap fill material to create a first cavity while the second portion of the gap fill material remains in place, depositing a first metal-containing substance in the first cavity, performing a second etching of the second portion of the gap fill material to create a second cavity while the first metal-containing substance remains in place, and depositing a second metal-containing substance in the second cavity.

Multi color stack for self aligned dual pattern formation for multi purpose device structures

Methods open etch stop layers in an integrated environment along with metallization processes. In some embodiments, a method for opening an etch stop layer (ESL) prior to metallization may include etching the ESL with an anisotropic process using direct plasma to form helium ions that are configured to roughen the ESL for a first duration of approximately 10 seconds to approximately 30 seconds, forming aluminum fluoride on the ESL using remote plasma and nitrogen trifluoride gas for a second duration of approximately 10 seconds to approximately 30 seconds, and exposing the ESL to a gas mixture of boron trichloride, trimethylaluminum, and/or dimethylaluminum chloride at a temperature of approximately 100 degrees Celsius to approximately 350 degrees Celsius to remove aluminum fluoride from the ESL and a portion of a material of the ESL for a third duration of approximately 30 seconds to approximately 60 seconds.

Methods for removing etch stop layers

A semiconductor processing method may include providing a fluorine-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region. The substrate may include an exposed region of silicon-and-oxygen-containing material. The substrate may include an exposed region of a liner material. The methods may include providing a hydrogen-containing precursor to the semiconductor processing region. The methods may include contacting the substrate with the fluorine-containing precursor and the hydrogen-containing precursor. The methods may include selectively removing at least a portion of the exposed silicon-and-oxygen-containing material.

Methods of highly selective silicon oxide removal

Embodiments of the present disclosure generally relate to a batch processing chamber that is adapted to simultaneously cure multiple substrates at one time. The batch processing chamber includes multiple processing sub-regions that are each independently temperature controlled. The batch processing chamber may include a first and a second sub-processing region that are each serviced by a substrate transport device external to the batch processing chamber. In addition, a slotted cover mounted on the loading opening of the batch curing chamber reduces the effect of ambient air entering the chamber during loading and unloading.

Batch curing chamber with gas distribution and individual pumping

Processing methods may be performed to expose a contact region on a semiconductor substrate. The methods may include selectively removing a first region of a silicon material between source/drain regions of a semiconductor substrate to expose a first region of oxide material. The methods may include forming a liner over the first region of oxide material and contacting second regions of the silicon material proximate the source/drain regions of the semiconductor substrate. The methods may also include selectively removing the second regions of the silicon material proximate the source/drain regions of the semiconductor substrate to expose a second region of the oxide material. The methods may further include selectively removing the second region of the oxide material from a surface of a contact in the semiconductor structure.

Replacement contact process

Exemplary methods of semiconductor processing may include providing a boron-and-carbon-and-nitrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include generating a capacitively-coupled plasma of the boron-and-carbon-and-nitrogen-containing precursor. The methods may include forming a boron-and-carbon-and-nitrogen-containing layer on the substrate. The boron-and-carbon-and-nitrogen-containing layer may be characterized by a dielectric constant below or about 3.5.

Low-k boron carbonitride films

Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) and corresponding methods. In an example, a film stack is formed on a substrate. The film stack includes multiple unit stacks, each having, sequentially, a first dielectric layer, a semiconductor layer, and a second dielectric layer. A first opening is formed through the film stack. The second dielectric layer is pulled back from the first opening forming a first lateral recess. A gate structure is formed in the first lateral recess and disposed on a portion of the semiconductor layer. A second opening, laterally disposed from where the first opening was formed, is formed through the film stack. The portion of the semiconductor layer is pulled back from the second opening forming a second lateral recess. A capacitor is formed in a region where the second lateral recess was disposed and contacting the portion of the semiconductor layer.

Three-dimensional dynamic random access memory (DRAM) and methods of forming the same

Examples of the present technology include semiconductor processing methods to form diffusion barriers for germanium in a semiconductor structure. The methods may include forming a semiconductor layer stack from pairs of Si-and-SiGe layers. The Si-and-SiGe layer pairs may be formed by forming a silicon layer, and then forming the germanium barrier layer of the silicon layer. In some embodiments, the germanium-barrier layer may be less than or about 20 &#x212b;. A silicon-germanium layer may be formed on the germanium-barrier layer to complete the formation of the Si-and-SiGe layer pair. In some embodiments, the silicon layer may be an amorphous silicon layer, and the SiGe layer may be characterized by greater than or about 5 atom % germanium. Examples of the present technology also include semiconductor structures that include a silicon-germanium layer, a germanium-barrier layer, and a silicon layer.

Diffusion barriers for germanium

Processing methods may be performed to form an airgap spacer on a semiconductor substrate. The methods may include forming a spacer structure including a first material and a second material different from the first material. The methods may include forming a source/drain structure. The source/drain structure may be offset from the second material of the spacer structure by at least one other material. The methods may also include etching the second material from the spacer structure to form the airgap. The source/drain structure may be unexposed to etchant materials during the etching.

Airgap formation processes

Hydrogen free (low-H) silicon dioxide layers are disclosed. Some embodiments provide methods for forming low-H layers using hydrogen-free silicon precursors and hydrogen-free oxygen sources. Some embodiments provide methods for tuning the stress profile of low-H silicon dioxide films. Further, some embodiments of the disclosure provide oxide-nitride stacks which exhibit reduced stack bow after anneal.

Hydrogen free silicon dioxide

Memory devices and methods of manufacturing memory devices are provided. Described are devices and methods where 3D pitch multiplication decouples high aspect ratio etch width from cell width, creating small cell active area pitch to allow for small DRAM die size.

3D pitch multiplication

Memory devices incorporating bridged word lines are described. The memory devices include a plurality of active regions spaced along a first direction, a second direction and a third direction. A plurality of conductive layers is arranged so that at least one conductive layer is adjacent to at least one side of each of the active regions along the third direction. A conductive bridge extends along the second direction to connect each of the conductive layers to one or more adjacent conductive layer. Some embodiments include an integrated etch stop layer. Methods of forming stacked memory devices are also described.

3-D DRAM structures and methods of manufacture

Growing community of inventors

San Jose, CA, United States of America

Nitin K Ingle