Intel Corporation

Nisha Ananthakrishnan

Arjun Krishnan

Yiqun Bai

Suriyakala Ramalingam

Yonghao Xiu

Sivakumar Nagarajan

Amram Eitan

Hsin-Yu Li

Yuying Wei

Nachiket R Raravikar

Robert M Nickerson

Vipul V Mehta

Purushotham Kaushik Muthur Srinath

Shripad Gokhale

Elizabeth Nofen

Gregory S Constable

Hitesh Arora

John Decker

Yang Guo

Nick Ross

Rahul N Manepalli

Saikumar Jayaraman

James Chris Matayabas, Jr

Edvin Cetegen

Dingying David Xu

Sandeep Razdan

Shan Zhong

Ziyin Lin

Liwei Wang

Hong Dong

Sushrutha Reddy Gujjula

Randall D Lowe, Jr

Craig Jonathan Weinman

Beverly J Canham

Sairam Agraharam

Xavier Francois Brun

Rajendra C Dias

Manish Dubey

Anna M Prakash

Kaizad Rumy Mistry

Rajen S Sidhu

Elah Bozorg-Grayeli

Vijay Wakharkar

Nirupama Chakrapani

Paul R Start

Shankar Ganapathysubramanian

Wei Tan

Kabirkumar Mirpuri

James C Matayabas

Venmathy McMahan

Michelle S Phen

Yawei Liang

Amrita Mallik

Janet Feng

Kuang-Han Chu

Jigneshkumar P Patel

Craig J Weinman

Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.

Microelectronics package comprising a package-on-package (PoP) architecture with inkjet barrier material for controlling bondline thickness and PoP adhesive keep out zone

Microelectronics package comprising a package-on-package (PoP) architecture with inkjet barrier material for controlling bondline thickness and pop adhesive keep out zone

Microelectronics package comprising a package-on-package (POP) architecture with inkjet barrier material for controlling bondline thickness and POP adhesive keep out zone

Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a plurality of first dies on a substrate, an encapsulation layer over the first dies and the substrate, an interface layer over the first dies and the encapsulation layer, and a passive heat spreader on the interface layer, wherein the interface layer thermally couples the first dies to the passive heat spreader. The passive heat spreader includes a silicon (Si) or a silicon carbide (SiC). The interface layer includes a silicon nitride (SiN) material, a silicon monoxide (SiO) material, a silicon carbon nitride (SiCN) material, or a thermal adhesive material. The semiconductor package may include a plurality of second dies and the substrate on a package substrate, a thermal interface material (TIM) over the second dies, the passive heat spreader, and the package substrate, and a heat spreader over the TIM and the package substrate.

Wafer level passive heat spreader interposer to enable improved thermal solution for stacked dies in multi-chips package and warpage control

A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die. An encapsulant is over the protrusion of the substrate, the encapsulant extending beneath the first die, and the encapsulant extending beneath the second die.

Micro-electronic package with substrate protrusion to facilitate dispense of underfill between a narrow die-to-die gap

A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die. The substrate protrusion can enable void-free underfill.

Some embodiments relate to an electronic package. The electronic package includes a first die and a second die stacked onto the first die. A first encapsulant is positioned between the first die and the second die. The first encapsulant includes a first material that covers a first volume between the first die and the second die. A second encapsulant is positioned between the first die and the second die. The second encapsulant includes a second material that covers a second volume between the first die and the second die. The first material has a higher thermal conductivity than the second material, and the second material more effectively promotes electrical connections between the first die and the second die as compared to the first material.

Two material high K thermal encapsulant system

Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include modifying an underfill material with one of a thiol adhesion promoter, an azole coupling agent, surface modified filler, and peroxide based cross-linking polymer chemistries to greatly enhance adhesion in package structures utilizing the embodiments herein.

Methods of promoting adhesion between underfill and conductive bumps and structures formed thereby

Techniques and mechanisms for mitigating warpage of structures in a package. In an embodiment, a packaged integrated circuit device includes a mold compound disposed at least partially around an integrated circuit chip. The mold compound comprises fibers suspended in a media that is to aid in mechanical reinforcement of such fibers. The reinforced fibers contribute to mold compound properties that resist warping of the IC chip that might otherwise take place as a result of solder reflow or other processing. A modulus of elasticity of the mold compound is equal to or more than three GigePascals (3 GPa), where the modulus of elasticity corresponds to a temperature equal to two hundred and sixty degrees Celsius (260&#xb0; C.). In another embodiment, a spiral flow value of the mold compound is equal to or more than sixty five centimeters (65 cm).

Mold compound with reinforced fibers

Methods for covalently and indelibly anchoring a polyacrylate polymer using a UV-induced polymerization process in the presence of a photoinitiator to an oxide surface are disclosed herein. The methods and compositions prepared by the methods can be used as indelible marking materials for use on microelectronic packages and as solder and sealant barriers to prevent overspreading of liquids on the oxide surfaces of microelectronic packages. The polyacrylate polymers are covalently linked to the oxide surface by use during the printing and UV-curing process of an adhesion promoter having as a first domain an oxide-reactive silyl group, bonded via a linker to an acrylate-reactive group.

Robust ink formulations for durable markings on microelectronic packages and its extendibility as a barrier material for thermal and sealant materials

Methods of forming microelectronic packaging structures and associated structures formed thereby are described. Those methods and structures may include forming a wafer level underfill (WLUF) material comprising a resin material, and adding at least one of a UV absorber, a sterically hindered amine light stabilizer (HALS), an organic surface protectant (OSP), and a fluxing agent to form the WLUF material. The WLUF is then applied to a top surface of a wafer comprising a plurality of die.

Methods of forming wafer level underfill materials and structures formed thereby

An underfill composition comprises a curable resin, a plurality of filler particles loaded within the resin, the filler particles comprising at least 50 weight % of the underfill composition. The filler particles comprise first filler particles having a particle size of from 0.1 micrometers to 15 micrometers and second filler particles having a particle size of less than 100 nanometers. A viscosity of the underfill composition is less than a viscosity of a corresponding composition not including the second filler particles.

Narrow-gap flip chip underfill composition

A fluxing-encapsulant material and method of use thereof in a thermal compression bonding (TCB) process is described. In an embodiment, the TCB process includes ramping the bond head to 250&#xb0; C.-300&#xb0; C. at a ramp rate of 50&#xb0; C./second-100&#xb0; C./second. In an embodiment, the fluxing-encapsulant material comprising one or more epoxy resins having an epoxy equivalent weight (EEW) of 150-1,000, a curing agent, and a fluxing agent having a mono-carboxylic acid or di-carboxylic acid and a pKa of 4-5.

Fluxing-encapsulant material for microelectronic packages assembled via thermal compression bonding process

Underfill materials for fabricating electronic devices are described. One embodiment includes an underfill composition including an epoxy mixture, an amine hardener component, and a filler. The epoxy mixture may include a first epoxy comprising a bisphenol epoxy, a second epoxy comprising a multifunctional epoxy, and a third epoxy comprising an aliphatic epoxy, the aliphatic epoxy comprising a silicone epoxy. The first, second, and third epoxies each have a different chemical structure. Other embodiments are described and claimed.

Flexible underfill compositions for enhanced reliability

Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having an underfill layer with filler particles arranged in a generally random distribution pattern. In some embodiments, a generally random distribution pattern of filler particles may be obtained by reducing an electrostatic charge on one or more components of the IC package assembly, by applying a surface treatment to filler to reduce filler electrical charge, by applying an electric force against the filler particles of the underfill material in a direction opposite to a direction of gravitational force, by using an underfill material with a relatively low maximum filler particle size, and/or by snap curing the underfill layer at a relatively low temperature. Other embodiments may be described and/or claimed.

Method for reducing underfill filler settling in integrated circuit packages

Growing community of inventors

Chandler, AZ, United States of America

Nisha Ananthakrishnan