Intersil Corporation

St Assembly Test Services Inc.

Bitblitz Communications, Inc.

Nirmal K Sharma

Hien Boon Tan

Jason Andrew Chen

Rahamat Bidin

Ge Gong

A method for enhancing thermal performance of an integrated circuit package attaches a dummy die to the semiconductor die of the integrated circuit. The dummy die is then thermally coupled through external terminals to the conductive layers of a printed circuit board. In one embodiment, the integrated circuit package includes an insulating substrate on which the dummy die is attached. Conductive vias thermally connect conductive terminals provided on one side of the insulating substrate to conductive terminals provided on the other side of the insulating substrate. In one embodiment, the integrated circuit package is provided as a ball grid array (BGA) package. In addition, multiple layers of conductors can be provided in both the insulating substrate of the integrated circuit and in the external printed circuit board.

Package for integrated circuit with thermal vias and method thereof

A method and an integrated circuit package support a high-speed integrated circuit operating at 10 GHz or higher switching speeds. The packaged integrated circuit has external terminals, a semiconductor die having conventional bonding pads, a substrate (e.g., printed circuit board) having conductive traces to couple input, output or bi-directional signals between bonding finger areas of the conductive traces and the external terminals. A ground plate that is electrically isolated from a conductive trace is positioned in the vicinity of the bonding finger area of the conductive trace. Bond wires connect the bonding pads of the electronic circuit and the bonding finger areas of the conductive traces. The ground plate improves integrity in a high-speed signal by canceling the complex impedance of a bond wire. In addition, the packaged integrated circuit can use multiple bond wires to connect the same bonding finger area of a conductive trace on the substrate and a corresponding bonding pad of the electronic circuit. The multiple bond wire approach reduces inductance in the bond wires.

Matched impedance bonding technique in high-speed integrated circuits

An embodiment of the invention in a quad flat no-lead package is described. The package is produced by encapsulating an integrated circuit chip, a die pad to which the chip is affixed, and leads which are connected to the chip in a molding compound. Leads are positioned on all four sides of the package, the exposed (bottom) portions of the leads are coplanar with the bottom of the package, and the leads do not extend, or extend only slightly, beyond the area of the package. The package includes a die pad also having an exposed (bottom) portion that is coplanar with the bottom of the package. The top portions of the leads are coplanar with the top surface of the die pad, and are flat.

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Fremont, CA, United States of America

Nirmal K Sharma