Infineon Technologies Ag

Other

Texas Instruments Corporation

Nirmal Chaudhary

Hong-Jyh Li

Thomas Schulz

Laertis Economikos

Richard Anthony Conti

David Edward Kotecki

Christian Cornelius Russ

Gerhard Kunkel

Weize W Xiong

Hua Shen

Fen Fen Jamin

Jenny Lian

Tobias Mono

Satish D Athavale

Craig Henry Huffman

Veit Klee

Ahmad Houssam Tarakji

Paul Schroeder

John Pohl

A new architecture to fabricate high-rise fully monolithic three-dimensional Integrated-Circuits (3D-ICs) is described. It has the major advantage over all known prior arts in that it substantially reduces RC-delays and fully eliminates or very substantially reduces the large and bulky electrically conductive Through-Silicon-VIAS in a monolithic 3D integration. This enables the 3D-ICs to have faster operational speed with denser device integration.

Approach to the manufacturing of monolithic 3-dimensional high-rise integrated-circuits with vertically-stacked double-sided fully-depleted silicon-on-insulator transistors

A transistor and method of manufacturing thereof. A gate dielectric and gate are formed over a workpiece, and the source and drain regions of a transistor are recessed. The recesses are filled with a dopant-bearing metal, and a low-temperature anneal process is used to form doped regions within the workpiece adjacent the dopant-bearing metal regions. A transistor having a small effective oxide thickness and a well-controlled junction depth is formed.

Transistor with dopant-bearing metal in source and drain

An electronic circuit and method for producing the electronic circuit, where the electronic circuit includes a functional circuit including at least one multigate functional field effect transistor and an ESD protection circuit including at least one multigate ESD protection field effect transistor. The multigate protection field effect transistor is a transistor that is partially depleted of electrical charge carriers, and the trigger voltage of the multigate protection field effect transistor is less than the trigger voltage of the multigate functional field effect transistor.

Electronic circuit, electronic circuit arrangement and method for producing an electronic circuit

In a method of forming a semiconductor device, a self-planarizing conductive layer is formed over a substrate that includes a topography having sharp drop-offs. The self-planarizing conductive layer is characterized by a substantially flatter surface than the underlying topography. As a result of the self-planarizing layer, a masking layer having a more uniform thickness may be formed over the conductive layer. Because the masking layer has a more uniform thickness, the masking layer may easily be patterned without causing damage to the underlying materials. These techniques may be used to fabricate, among other things, a FinFET without parasitic spacers formed around the fins and the source/drain regions.

Gate electrode for FinFET device

A nitride hard mask ( ) is used to isolate active areas of a DRAM cell. The shallow trench isolation (STI) method includes forming memory cells comprising deep trenches ( ) on a semiconductor wafer ( ). The memory cell deep trenches ( ) are separated from active areas ( ) by a region of substrate ( ). A nitride hard mask ( ) is formed over the semiconductor wafer ( ). The wafer ( ) is patterned with the nitride hard mask ( ), and the wafer ( ) is etched to remove the region of substrate ( ) between the deep trenches and active areas to provide shallow trench isolation. An etch chemistry selective to the nitride hard mask ( ) is used.

Self-aligned STI process using nitride hard mask

Reactive ion etch (RIE) selectivity during etching of a feature nearby embedded structure is improved by using a silicon oxynitride layer formed with carbonization throughout layer.

Low temperature carbon rich oxy-nitride for improved RIE selectivity

A method for forming an electrode. The method includes forming a conductive plug through a first dielectric layer. The plug extends from an upper surface of the first dielectric layer to a contact region in a semiconductor substrate. The electrode is formed photolithographically, misalignment of a mask registration in the photolithography resulting in exposing surface portions of the barrier contact. A second dielectric layer is deposited over the first dielectric layer, over side portions and top portions of the formed electrode, and over the exposed portions of barrier contact. A sacrificial material is provided on portions of the second dielectric layer disposed on lower sides of the, electrode, on portions of the second dielectric layer disposed on the first dielectric layer, and on said exposed portions of the barrier contact while exposing portions of the second dielectric layer on the top portions and upper side portions of the formed electrode. The exposed portions of the second dielectric layer are removed while leaving the portions of the second dielectric layer on the exposed portions of the barrier contact. A material is deposited over exposed portions of the first electrode and over remaining portions of the second dielectric layer in an oxidizing environment. A second electrode is formed for the storage element over the material. In forming a capacitor storage element, the portion of the second dielectric layer on the barrier contact prevents oxidation of the barrier contact during the material formation process.

Semiconductor structure and manufacturing method

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Austin, TX, United States of America

Nirmal Chaudhary