Sandisk Corporation

Sandisk Technologies Inc.

Sandisk 3d LLC

Sandisk Il Ltd.

Sandisk Ii, Ltd.

Sandick Technologies Inc.

Nima Mokhlesi

Deepak Chandra Sekar

Yupin K Fong

Daniel C Guterman

Henry Chin

Jeffrey W Lutze

Dengtao Zhao

Masaaki Higashitani

Man Lung Mui

Yan Li

Eran Sharon

Roy E Scheuerlein

Seungpil Lee

Hao Nguyen

George Matamis

Hock C So

Tapan Samaddar

Yingda Dong

Idan Alrod

Dana Lee

Tuan Duc Pham

Henry Chien

Mohan Dunga

Geoffrey Steven Gongwer

Hidetaka Horiuchi

Gerrit Jan Hemink

Raul-Adrian Cernea

Klaus Florian Schuegraf

Jun Wan

Toru Miwa

Anubhav Khandelwal

Shahzad Khalid

Prashanti Govindu

Lanlan Gu

James K Kai

Takashi Whitney Orimoto

Deepak Raghu

Ali K Al-Shamma

Gen Pei

Itshak Afriat

Alexander Chu

John Pasternak

Eron Sharon

Ashish Pal Singh Ghai

A process is performed periodically or in response to an error in order to dynamically and adaptively optimize read compare levels based on memory cell threshold voltage distribution. One embodiment of the process includes determining threshold voltage distribution data for a population of non-volatile storage elements, smoothing the threshold voltage distribution data using a weighting function to create an interim set of data, determining a derivative of the interim set of data, and identifying and storing negative to positive zero crossings of the derivative as read compare points.

Dynamic and adaptive optimization of read compare levels based on memory cell threshold voltage distribution

A series of programming pulses, where the individual pulses are identified by a pulse number, is used to program a page of memory cells in parallel. After receiving a pulse, the memory cells under verification are verified to determine if they have been programmed to their respective target states. The memory cells that have been verified are inhibited from further programming while those memory cells not verified will be further programmed by subsequent programming pulses. The pulsing, verification and inhibition continue until all memory cells of the page have been program-verified. Each verify level used in the verification is a function of both the target state and the pulse number. This allows adjustment of the verify level to compensate for changes in sensing, including those due to variation in source line loading during the course of programming.

Programming of nonvolatile memory with verify level dependent on memory state and programming loop count

A non-volatile storage system stores data by programming the data as binary data into blocks that have not yet been programmed with multi-state data and have not yet been programmed with binary data X times. The system transfers data from multiple blocks (source blocks) of binary data to one block (target block) of multi-state data using a multi-state programming process, where the target block has been previously programmed with binary data X times (or less than X times).

Programming non-volatile storage using binary and multi-state programming processes

A three dimensional stacked non-volatile memory device comprises alternating dielectric layers and conductive layers in a stack, a plurality of bit lines below the stack, and a plurality of source lines above the stack. There is a separate source line for each bit line. Each source lines is connected to a different subset of NAND strings. Each bit line is connected to a different subset of NAND strings. Multiple data states are verified concurrently. Reading is performed sequentially for the data states. The data states are programmed concurrently with memory cells being programmed to lower data states having their programming slowed by applying appropriate source line voltages and bit line voltages.

Three dimensional non-volatile memory with separate source lines

A non-volatile storage system dedicates a subset of blocks to be used for shorting source lines to bit lines at periodic positions along the bit lines during certain memory operations.

Three dimensional non-volatile memory with shorting source line/bit line pairs

Methods and devices for simultaneously verifying or reading multiple states in non-volatile storage are disclosed. Methods and devices for efficiently reducing or eliminating cross-coupling effects in non-volatile storage are disclosed. Methods and devices for efficiently performing reads at a number of voltages to search for the threshold voltage of a memory cell are disclosed. Memory cells on different NAND strings that are read at the same time may be tested for different threshold voltage levels. Memory cells may be tested for different threshold voltages by applying different gate-to-source voltages to memory cells being tested for different threshold voltages. Memory cells may be tested for different threshold voltages by applying different drain to source voltages to the memory cells. Different amounts of compensation for cross-coupling affects may be applied to memory cells on different NAND strings that are read or programmed at the same time.

Simultaneous multi-state read or verify in non-volatile storage

Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased or decreased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage.

Reducing energy consumption when applying body bias to substrate having sets of NAND strings

A non-volatile memory system includes a plurality of non-volatile memory cells, one or more control circuits that perform programming of the memory cells, a power supply line that provides a supply used to program the memory cells, and a current measurement circuit. The current measurement circuit senses an indication of current on the power supply line. The one or more control circuits determine whether the programming of the memory cells is successful based on the indication of current.

Three dimensional non-volatile memory with current sensing programming status

A system and methods to find the threshold voltage distribution across a set of nonvolatile memory cells, such that embodiments may incorporate this distribution information into calculations that may change the read compare voltages used to read the memory cells, while ensuring adequate separation in read voltage between different data states at which the memory cells may be read.

Dynamic adjustment of read voltage levels based on memory cell threshold voltage distribution

Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To account for this coupling, the read process for a particular memory cell will provide compensation to an adjacent memory cell in order to reduce the coupling effect that the adjacent memory cell has on the particular memory cell.

Read operation for non-volatile storage with compensation for coupling

A non-volatile storage system is disclosed that includes pairs of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. To operate the system, two selection lines are used so that the NAND strings (or other groupings of memory cells) sharing a bit line can be selected at the block level. Both selection lines are connected to a selection gate for each of the NAND strings (or other groupings of memory cells) sharing the bit line. One set of embodiments avoid unwanted boosting during read operations by keeping the channels of the memory cells connected to word lines on the drain side of the selected word line biased at a fixed potential.

Operation for non-volatile storage system with shared bit lines

A non-volatile memory has its cells' thresholds programmed within any one of a first set of voltage bands partitioned by a first set of reference thresholds across a threshold window. Hard bits are obtained when read relative to the first set of reference thresholds. The cells are read at a higher resolution relative to a second set of reference thresholds so as to provide additional soft bits for error correction. The soft bits are generated by a combination of a first modulation of voltage on a current word line WLn and a second modulation of voltage on an adjacent word line WLn+1, as in a reading scheme known as 'Direct-Lookahead (DLA)'.

Non-volatile memory and methods with soft-bit reads while reading hard bits with compensation for coupling

Methods and devices for simultaneously verifying or reading multiple states in non-volatile storage are disclosed. Methods and devices for efficiently reducing or eliminating cross-coupling effects in non-volatile storage are disclosed. Methods and devices for efficiently performing reads at a number of voltages to search for the threshold voltage of a memory cell are disclosed. Memory cells on different NAND strings that are read at the same time may be tested for different threshold voltage levels. Memory cells may be tested for different threshold voltages by applying different gate-to-source voltages to memory cells being tested for different threshold voltages. Memory cells may be tested for different threshold voltages by applying different drain to source voltages to the memory cells. Different amounts of compensation for cross-coupling affects may be applied to memory cells on different NAND strings that are read or programmed at the same time. A binary search may be performed.

Reading soft bits simultaneously

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Los Gatos, CA, United States of America

Nima Mokhlesi