Mentor Graphics Corporation

Other

Siemens Industry Software Gmbh

Siemens Product Lifecycle Management Software Inc.

Siemens Industry Software Nv

Nilanjan Mukherjee

Janusz Rajski

Jerzy Tyszer

Mark A Kassab

Grzegorz Mrugalski

Dariusz Czysz

Wu-Tung Cheng

Elham K Moghaddam

Jonathan Makem

Xiaogang Du

Justyna Zawada

Yu Jane Huang

Jedrzej Solecki

Jakub Janicki

Yingdi Liu

Amit Kumar

Chen Wang

Xijiang Lin

Thomas Hans Rinderknecht

Artur Pogiel

Avijit Dutta

Ronald Press

Joseph C Rayhawk

Sylwester Milewski

Paul J Reuter

Mohamed Dessouky

Yahya M Z Mustafa

Sudhakar Mannapuram Reddy

Lukasz Rybak

Jay Babak Jahangiri

Chien-Chung Tsai

Omer Ghazi Samman

Debashis Basu

Abinesh Thota

Harold Fogg

Bartosz Wlodarczak

Jean Cabello

Wafa Daldoul

Janusz Rasjki

Jeffrey Mayer

Przemyslaw Szczerbicki

Amrendra Kumar

Jansuz Rajski

Jerin Joe

Irith Pomeranz

Mrugalski Grzegorz

Tyszer Jerzy

Janicki Jakub

A computer-implemented method of modifying a finite element mesh. The method includes providing an original-input-orphan-mesh, selecting and extracting at least a part of the original-input-orphan-mesh as an orphan-element-patch-object, generating faces on the orphan-element-patch-object as a faces-on-mesh-object geometry, generating a new mesh patch element based on the faces-on-mesh-object-geometry and at least one changed meshing-parameter. The changed meshing-parameter is assigned to generate a new mesh patch element that is different to the corresponding original-input-orphan-mesh. The method further includes generating an amended orphan mesh by replacing the orphan-element-patch-object of the original-input-orphan-mesh by the new mesh patch element.

Modifying a finite element mesh

A circuit comprises scan gating devices inserted between outputs of scan chains and inputs of a test response compactor. The scan gating devices divides the scan chains into groups of scan chains. Each of the scan gating devices operates in either an enabled mode or a disenabled mode based on a first signal. A scan gating device operating in the enabled mode blocks, blocks only at some clock cycles, or does not block a portion of a test response of a test pattern captured by and outputted from a scan chain in the associated scan chain group based on a second signal. Scan gating devices operating in the disenabled mode do not block, or based on a third signal, either block or do not block, a portion of the test response captured by and outputted from all scan chains in each of the associated scan chain groups.

Universal compactor architecture for testing circuits

Methods for CAD operations and corresponding systems () and computer-readable mediums () are disclosed herein. A method () includes receiving model data () of a surface () of a part () to be manufactured. The method includes performing a loop-paving process () for a first portion of the surface () to produce a first set of elements (). The method includes performing a Cartesian meshing process () for a second portion of the surface () to produce a second set of elements (). The method includes performing a subdivision meshing process () for a third portion of the surface () to produce a third set of elements (). The method includes combining () the first set of elements (), the second set of elements (), and the third set of elements () to produce a final mesh () for the surface () of the part () to be manufactured.

Multizone quadrilateral mesh generator for high mesh quality and isotropy

A circuit comprises: a bit-flipping signal generation device comprising a storage device and configured to generate a bit-flipping signal based on bit-flipping location information, the storage device configured to store the bit-flipping location information for a first number of bits, the bit-flipping location information obtained through a fault simulation process; a pseudo random test pattern generator configured to generate test patterns based on the bit-flipping signal, the pseudo random test pattern generator comprising a register configured to be a linear finite state machine, the register comprising storage elements and bit-flipping devices, each of the bit-flipping devices coupled to one of the storage elements; and scan chains configured to receive the test patterns, wherein the bit-flipping signal causes one of the bit-flipping devices to invert a bit of the register each time a second number of test patterns is being generated by the pseudo random test pattern generator during a test.

Trajectory-optimized test pattern generation for built-in self-test

A system for testing a circuit comprises scan chains, a controller configured to generate a bit-inverting signal based on child test pattern information, and bit-inverting circuitry coupled to the controller and configured to invert bits of a parent test pattern associated with a plurality of shift clock cycles based on the bit-inverting signal to generate a child test pattern during a shift operation. Here, the plurality of shift clock cycles for bit inverting occur every m shift clock cycles, and the child test pattern information comprises information of m and location of the plurality of shift clock cycles in the shift operation.

Deterministic stellar built-in self test

Methods for CAD operations and corresponding systems () and computer-readable mediums () are disclosed herein. A method includes receiving () a model () of a part to be manufactured, wherein the model includes a plurality of original faces (). The method includes classifying () each face in model according to a relative face curvature according to classifications that include at least a high-curvature classification (). The method includes classifying () any sliver faces () and narrow blend faces () of the plurality of faces. The method includes merging () contiguous faces () in each classification. The method includes detecting () special faces () of the plurality of faces. The method includes restoring () original faces in the high-curvature classification except for the special faces (). The method includes processing () shared edges of the restored original faces to produce merged faces (). The method includes merging together () any merged faces that produce a locally narrow face () or an isthmus (). The method includes storing () a modified model of the part to be manufactured.

Feature based abstraction and meshing

A circuit comprises: a register configured to be a linear finite state machine and comprising storage elements, injection devices, one or more input channels for injecting variables using the injection devices, and one or more feedback devices; a plurality of phase shifters, each of the plurality of phase shifters configured to receive signals from a unique segment of the register; scan chains, serial inputs of the scan chains configured to receive signals from outputs of the plurality of phase shifters, wherein the one or more input channels are coupled to the injection devices at injection points in the register, each of the injection points being assigned to one of the one or more input channels based on lifespan values for the injection points, the injection points being determined based on one or more predetermined requirements.

Layout-friendly test pattern decompressor

A system and method is provided for element quality improvement in three-dimensional (3D) quadrilateral-dominant surface meshes. The system may include a processor configured to collapse a first plurality of edges of a plurality of quadrilateral elements that form a surface mesh of a 3D model, which edges have lengths that are shorter than a predetermined fraction of a minimum element edge length (MEL). Further, the processor may also move nodes connected to at least some of a second plurality of edges of the plurality of quadrilateral elements so as to have lengths that are at least the MEL. Also, the processor may adjust included angles and the warp of elements to be within predetermined limits. Further, the processor may collapse in the mesh all remaining edges of the plurality of quadrilateral elements that are shorter than the MEL to produce a modified surface mesh in which all quadrilaterals in the modified mesh have edge lengths that are at least the MEL.

System and method for element quality improvement in 3D quadrilateral-dominant surface meshes

A scan cell comprises: a state element and selection and combination circuitry. The selection and combination circuitry comprises first combination circuitry configured to combine a signal from a scan input of the scan cell with a signal from a functional circuit input of the scan cell to generate a first signal, second combination circuitry configured to combine the signal from the functional circuit input of the scan cell with an output signal of the state element to generate a second signal, and selection circuitry configured to select an input signal for the state element from the signal from the scan input of the scan cell, the signal from the functional circuit input of the scan cell, the first signal, and the second signal based on two selection input signals of the scan cell.

Scan cell architecture for improving test coverage and reducing test application time

A system and method is provided that facilitates generating meshes for object models of structures for use with finite element analysis simulations carried out on the structure. The system may include at least one processor configured to classify a type of an input face of a three dimensional (3D) object model of a structure based at least in part on a number of loops included by the input face. The processor may also select based on the classified type of the input face a multi-block decomposition algorithm from among a plurality of multi-block decomposition algorithms that the processor is configured to use. Further the processor may use the selected multi-block decomposition algorithm to determine locations of a plurality of blocks across the input face. In addition the processor may mesh each block to produce mesh data defining a mesh that divides the input face into a plurality of quadrilateral elements.

Mesh generation system and method

Disclosed are representative embodiments of methods, apparatus, and systems for test scheduling and test access in a test compression environment. Clusters of test patterns for testing a plurality of cores in a circuit are formed based on test information that includes compressed test data, corresponding tester channel requirements and correlated cores. The formation of test pattern clusters is followed by tester channel allocation. A best-fit scheme or a balanced-fit scheme may be employed to generate channel allocation information. A test access circuit for dynamic channel allocation can be designed based on the channel allocation information.

Test scheduling and test access in test compression environment

Various aspects of the disclosed technology relate to using capture-per-cycle test points to reduce test application time. A scan-based testing system includes a plurality of regular scan chains and one or more capture-per-cycle scan chains on which scan cells capture and compact test responses at predetermined observation points per shift clock cycle.

Test application time reduction using capture-per-cycle test points

Various aspects of the disclosed technology relate to conflict-reducing test point insertion techniques. Locations in a circuit design for inserting test points are determined based on internal signal conflicts caused by detecting multiple faults with a single test pattern. Test points are then inserted at the locations. The internal signal conflicts may comprise horizontal conflicts, vertical conflicts, or both. The test points may comprise control points, observation points, or both.

Test point insertion for low test pattern counts

Various aspects of the disclosed technology relate to techniques of using control test points to enhance hardware security. The design-for-security circuitry reuses control test points, a part of design-for-test circuitry. The design-for-security circuitry comprises: identity verification circuitry; scrambler circuitry coupled; and test point circuitry. The test point circuitry comprises scan cells and logic gates The identify verification circuitry outputs an identity verification result to the scrambler circuitry to enable/disable control test points of the test point circuitry through the logic gates, and the scrambler circuitry outputs logic bits for loading the scan cells to activate/inactivate the control test points through the logic gates.

Test point-enhanced hardware security

A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.

Continuous application and decompression of test patterns and selective compaction of test responses

Growing community of inventors

Wilsonville, OR, United States of America

Nilanjan Mukherjee