Tokyo Electron Limited

Other

Tokyo Eelctron Limited

Nihar Mohanty

Angelique Denise Raley

Subhadeep Kal

Anton J deVillers

Jeffrey Smith

Aelan Mosden

Kandabara N Tapily

Akiteru Ko

Scott W Lefevre

Eric Chih-Fang Liu

Lior Huli

Richard Farrell

Elliott Franke

Chi-Chun Liu

David L O'Meara

Vikas Berry

David S Moore

Sophie Thibaut

Satoru Nakamura

Cheryl Pereira

Angélique D Raley

An additional non-photoresist layer may be formed on patterned photoresist layers. The additional layer may be preferentially formed on the tops of the photoresist layer versus the sidewalls of the photoresist layer. In addition, the additional layer may be preferential formed on the tops of the photoresist layer versus exposed surfaces of layers underlying the photoresist layer. In this manner, the patterned structures formed by the photoresist layer are less likely to have line opens due to photoresist height variability or the relative thinness of the photoresist height used. Further, the formation of the additional layer may be through a cyclic deposition/trim process. The trim step of the cyclic process may also serve as a descum step that helps reduce line bridging and scumming. In one embodiment, the additional non-photoresist layer may be an organic polymer layer.

Method for reducing lithography defects and pattern transfer

A method for the dry removal of a material on a microelectronic workpiece is described. The method includes receiving a workpiece having a surface exposing a target layer composed of silicon and either (1) organic material or (2) both oxygen and nitrogen, and selectively removing at least a portion of the target layer from the workpiece. The selective removal includes exposing the surface of the workpiece to a chemical environment containing N, H, and F at a first setpoint temperature to chemically alter a surface region of the target layer, and then, elevating the temperature of the workpiece to a second setpoint temperature to remove the chemically treated surface region of the target layer.

Gas phase etch with controllable etch selectivity of Si-containing arc or silicon oxynitride to different films or masks

A method and system for the dry removal of a material on a microelectronic workpiece are described. The method includes receiving a workpiece having a surface exposing a target layer to be at least partially removed, placing the workpiece on a workpiece holder in a dry, non-plasma etch chamber, and selectively removing at least a portion of the target layer from the workpiece. The selective removal includes operating the dry, non-plasma etch chamber to perform the following: exposing the surface of the workpiece to a chemical environment at a first setpoint temperature in the range of 35 degrees C. to 100 degrees C. to chemically alter a surface region of the target layer, and then, elevating the temperature of the workpiece to a second setpoint temperature at or above 100 degrees C. to remove the chemically treated surface region of the target layer.

Gas phase etching system and method

Provided is a method for patterning a substrate, comprising: forming a layer of radiation-sensitive material on a substrate; preparing a pattern in the layer of radiation-sensitive material using a lithographic process, the pattern being characterized by material structures having a critical dimension (CD) and a roughness; following the preparing the pattern, performing a shrink process to reduce the CD to a reduced CD; and performing a growth process to grow the reduced CD to a target CD. Roughness includes a line edge roughness (LER), a line width roughness (LWR), or both LER and LWR. Performing the shrink process comprises: coating the pattern with a hard mask, the coating generating a hard mask coated resist; baking the hard mask coated resist in a temperature range for a time period, the baking generating a baked coated resist; and developing the baked coated resist in deionized water.

Extreme ultra-violet sensitivity reduction using shrink and growth method

A semiconductor device herein includes doped extension regions for silicon and silicon germanium nanowires. The nanowires can be selectively grown and recessed into a gate spacer. The semiconductor device can include a gate structure including the gate spacer; the nanowire or channel extending through the gate structure such that an end of the channel is recessed within a recess in said gate spacer; an extension region in contact with the end of the channel within the recess, the extension region being formed of an extension material having a different composition than a channel material of the channel such that a strain is provided in the channel; and a source-drain contact in contact with the extension region and adjacent to the gate structure.

Extension region for a semiconductor device

Embodiments of the invention provide a substrate processing method for bottom-up formation of a film in a recessed feature. According to one embodiment, the method includes providing a substrate containing a first layer and a second layer on the first layer, the second layer having a recessed feature extending through the second layer, and depositing a non-conformal mask layer on the substrate, where the mask layer has an overhang at an opening of the recessed feature. The method further includes removing the mask layer from a bottom of the recessed feature, while maintaining at least a portion of the overhang at the opening, selectively depositing a film on the bottom of the recessed feature, and removing the mask layer overhang from the substrate. The processing steps may be repeated at least once until the film has a desired thickness in the recessed feature.

Method for bottom-up formation of a film in a recessed feature

A method of forming a semiconductor device having a channel and a source-drain coupled to the channel. The method includes etching a channel region such that an end of the channel region forms a recess within a gate structure surrounding the channel region. An extension region is formed in contact with the channel region and at least partially filling the recess. Extension material of the extension region has a different composition from channel material of the channel region such that a strain is caused in the channel region. A source-drain region is in contact with the extension region and adjacent to the gate structure.

Techniques herein enable integrating stack materials and multiple color materials that require no corrosive gases for etching. Techniques enable a multi-line layer for self-aligned pattern shrinking in which all layers or colors or materials can be limited to silicon-containing materials and organic materials. Such techniques enable self-aligned block integration for 5 nm back-end-of-line trench patterning with an all non-corrosive etch compatible stack for self-aligned block. Embodiments include using lines of a same material but at different heights to provided etch selectivity to one of several lines based on type of material and/or height of material and etch rate.

Method for patterning a substrate using a layer with multiple materials

Provided is a method of patterning spacers, the method comprising: providing an initial patterned structure in a substrate in a processing chamber, the initial patterned structure comprising an organic mandrel and an underlying layer; exposing the patterned structure in a direct current superposition (DCS) plasma treatment process, the process depositing a layer of a first material on the initial patterned structure; performing an atomic layer conformal deposition process using a second material, the first material providing protection to the organic mandrel at the beginning of the atomic layer conformal deposition process; performing a spacer etch mandrel pull process, the process creating a final patterned structure with a target final sidewall angle; concurrently controlling integration operating variables in the DCS plasma treatment process, the atomic layer conformal deposition process, and the spacer etch mandrel pull process in order to meet the target final sidewall angle and other integration objectives.

Organic mandrel protection process

A formed back-end-of-line (BEOL) metal line layer may include a plurality of metal lines with dielectric oxide caps that are disposed in between each metal lines. To overlay an interconnecting layer of metal lines on a selected metal line of the BEOL metal line layer, a block copolymer (BCP) may be formed on a patterning layer. Thereafter, a selective etching of the formed BCP creates a recess above the selected metal line. The created recess facilitates the overlaying of the interconnecting layer of metal lines.

Method for fully self-aligned via formation using a directed self assembly (DSA) process

Techniques herein include a method of patterning a substrate that uses a self-alignment based process to align a via to odd and even trenches by using multiple different materials. Methods herein decompose or separate a via pattern into spacer side via and mandrel side via, and then sequentially access the spacer side and mandrel side respectively. With such a technique, overlay of via to grid is significantly improved. By using an additional memorization layer underneath a trench memorization layer and independently accessing the spacer side and mandrel side in the midst of a trench pattern, significant improvement in via alignment is achieved.

Method of reducing overlay error in via to grid patterning

A multiple patterning process is provided with a self-aligned blocking (SAB) technique. The SAB technique trades off difficult overlay requirements for more manageable etch selectivity requirements between the various layers utilized for the patterning process. As disclosed herein, damage to sidewalls resulting from etching at the self-aligned block masking step may still occur. Damage is repaired by providing a plug layer that fills the areas of the damaged spacers. The plug layer may be the same material as forms the spacers. In this manner, the fill process provides a self-healing mechanism for damaged spacers.

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Clifton Park, NY, United States of America

Nihar Mohanty