Nxp Usa, Inc.

Nihaar N Mahatme

Anirban Roy

Alexander Hoefler

Srikanth Jagannathan

Brad John Garni

Mehul D Shroff

Jon Scott Choy

Glenn Charles Abeln

Shayan Zhang

Kumar Abhishek

Lawrence Loren Case

Jeffrey C Cunningham

Rakesh Pandey

Nishant Lakhera

Akhilesh Kumar Singh

Uzi Zangi

Chee Seng Foong

Thomas Stephen Harp

Andrew Jefferson Mawer

Geoffrey Mark Lees

A data processing system includes a dynamic random access memory (DRAM), a prefetcher, and a refresh controller. The DRAM includes a plurality of DRAM cells, each with a capacitive storage element. The prefetcher is configured to prefetch information from the DRAM into a prefetch buffer in accordance with a prefetch pattern of addresses in the DRAM. The refresh controller includes a dynamic refresh control circuit configured to detect prefetch patterns of the prefetcher, and, in response to a detected prefetch pattern, refresh locations of the DRAM in accordance with a refresh pattern of addresses which is based on the prefetch pattern of addresses.

Refresh operations in embedded dynamic random access memories (DRAMs)

A magnetoresistive random access memory (MRAM) array includes MRAM cells, each MRAM cell having a corresponding Magnetic Tunnel Junction (MTJ) capable of being in a blown state or non-blown state, in which the blown state corresponds to a permanent breakdown of a tunnel dielectric layer of the corresponding MTJ. Write circuitry performs a one-time-programmable (OTP) write operation to blow selected MRAM cells. For each MRAM cell being blown, the write circuitry uses an initial OTP program reference for the MRAM cell being blown to detect onset of tunnel dielectric breakdown after application of each OTP write pulse of the OTP write operation. After detection of the onset, the write circuitry updates the initial OTP program reference, applies at least one additional OTP write pulse to the MRAM cell being blown, and uses the updated OTP program reference to verify that current saturation of the MRAM cell being blown has occurred.

Memory with one-time programmable (OTP) cells

A magnetoresistive random access memory (MRAM) array includes a data array and a sensor array. Each MRAM cell includes a Magnetic Tunnel Junction (MTJ). Each MRAM cell of the data array stores a data bit. A first and second column of the sensor array are connected to form a sensor column which includes sensor cells, each formed by a first MRAM cell in the first column together with a second MRAM cell in the second column along a same word line. Only one of a first MTJ of the first MRAM cell or second MTJ of the second MRAM cell is used as an MTJ of the sensor cell, and drain electrodes of select transistors of the first and second MRAM cells are electrically connected. Read circuitry provides read data from the data array and a sensor output indicative of a rupture state of an MTJ of the sensor array.

Magnetoresistive random access memory (MRAM) with end of life margin sensor

An array of bit cells is programmed with user data, each row including a corresponding word line and each column including a corresponding column line. The array includes a plurality of differential PUF bits, each having a first and second bit cell programmed with user data. A first set of sense-amplifiers outputs a set of data bits of the user data, and a second set of sense-amplifiers outputs a set of differential bits, each differential bit based on a differential current between two columns lines of the selected column lines corresponding to the first and second bit cells of a corresponding differential PUF bit along the selected word line. A potential PUF bit generator outputs a set of potential PUF bits based on the set of data bits of the user data from the first set of sense-amplifiers and the set of differential bits from the second set of sense-amplifiers.

Reusing memory arrays for physically unclonable function (PUF) generation

A semiconductor device comprises a substrate including a set of interconnect pads, a die mounted on the substrate, wherein the die includes circuitry that cannot withstand typical lead-free (Pb-free) solder reflow temperature during reflow process, and a reinforcing interposer including a first set of interconnect pads and a second set of interconnect pads. Low temperature solder material connects one of the set of interconnect pads on the substrate to a corresponding one of the first set of interconnect pads on the reinforcing interposer. A printed circuit board includes a set of interconnect pads. Low temperature solder material connects one of the set of interconnect pads of the printed circuit board to a corresponding one of the second set of interconnect pads of the reinforcing interposer. The low temperature solder material has a reflow temperature below typical Pb-free solder material.

Packaged semiconductor device assembly

A magnetoresistive random-access memory (MRAM) device includes an array of MRAM bit cells grouped into words, each word having specified number of data bit cells, error correction code (ECC) bit cells, and at least two inversion indicator bit cells, the inversion indicator bit cells being redundant of each other; and a memory controller. The memory controller is configured to, for each of the words, set the inversion indicator bit cells to indicate whether the number of data bit cells in a word having a zero value is greater than the number of data bit cells having a one value, invert the zeroes and ones in the bit cells when the inversion indicator bit cells are set to indicate a greater number of zeroes than ones in the data bit cells of the word, and revert the data bit cells to their value before the zeroes and ones were inverted.

Error rate reduction in a non-volatile memory (NVM), including magneto-resistive random access memories (MRAMS)

Error rate reduction in a non-volatile memory (NVM), including magneto-resistive random access memories (MRAMs)

A plurality of memory cells, in which each memory cell includes two corresponding supply terminal inputs, is powered up while applying a voltage differential between the corresponding supply terminal inputs for each of the plurality of memory cells. After powering up, the plurality of memory cells is read and a physically unclonable function (PUF) response is generated from data of the reading.

SRAM based physically unclonable function and method for generating a PUF response

A physically unclonable function (PUF) includes an array of differential PUF bits arranged in rows and columns, wherein each differential bit is located at an intersection of a row and a column, and includes a first PUF cell coupled to a corresponding first bit line and first source line and a second PUF cell coupled to a corresponding second bit line and second source line. The PUF includes a source bias transistor coupled between each corresponding first source line and a first power supply terminal and between each corresponding second source line and the first power supply terminal, wherein a gate electrode of each of the source bias transistors is coupled to a second power supply terminal, and a corresponding set of margin transistors coupled in parallel with each source bias transistor, wherein a gate electrode of each margin transistor is coupled to receive a corresponding margin setting control signal.

Physically unclonable function having source bias transistors

A packaged integrated circuit includes a photodiode and a memory. The photodiode generates energy when radiation strikes a surface of the photodiode. The memory includes a plurality of non-volatile memory cells and memory control circuitry. The memory control circuitry is configured to perform an operation to change values stored in at least some of the memory cells of the plurality of non-volatile memory cells while being powered by energy generated by the photodiode. An encapsulant at least partially encapsulates the photodiode and the memory, in which the encapsulant blocks radiation from reaching the surface of the photodiode.

Packaged integrated circuit having a photodiode and a resistive memory

A circuit includes a glitch measurement circuit and a glitch profile circuit. The glitch measurement circuit includes a first comparator to compare a glitch in a power supply voltage to a first threshold voltage, a first counter to generate a first count indicative of a time duration the first comparator indicates that the glitch trips the first threshold voltage, a second comparator to compare the glitch in the power supply voltage to a second threshold voltage different than the first threshold voltage, and a second counter to generate a second count indicative of a time duration the second comparator indicates that the glitch trips the second threshold voltage. The glitch profile circuitry utilizes the first count and the second count to generate a multi-voltage profile of the glitch, wherein the multi-voltage profile includes indications of the time durations indicated by the first count and the second count.

Glitch profiling in an integrated circuit

A data processing system and method for generating a digital code for use as a physically unclonable function (PUF) response is provided. The method includes activating a plurality of word lines for a read operation. A first bit line is coupled to a first input of a comparator during the read operation. A second bit line is coupled to a second input of the comparator during the read operation. A current is generated on each of the first and second bit lines. The currents on the first and second bit lines are converted to voltages. The voltage on the first bit line is compared to the voltage on the second bit line. A logic bit is output from the comparator as part of the digital code, a logic state of the logic bit is determined in response to the comparison. By selecting multiple word lines to determine a PUF response, noise immunity is improved.

Data processing system and method for generating a digital code with a physically unclonable function

A data system includes an information bus, a volatile memory located on the information bus, and an MRAM located on the information bus. The data system includes threat detection circuitry. In response to a threat condition to the MRAM, data is transferred via the information bus from the MRAM to the volatile memory for storage during a threat to the MRAM as indicated by the threat condition. In some examples, the threat condition is characterized as a magnetic field exposure.

Tamper protection of memory devices on an integrated circuit

An integrated circuit includes a magneto resistive RAM (MRAM) array having a plurality of MRAM cells, and a set of at least one Hall sensor circuit, each of the set including a Hall sensor to detect a magnetic field. The integrated circuit also includes magnetic processing circuitry for receiving at least one indication from the set of at least one Hall sensor circuit. The magnetic processing circuitry including an output to provide an indication of a possible magnetic field threat to the MRAM array based on the at least one indication from the set.

Magnetic attack detection in a magnetic random access memory (MRAM)

A data processing system includes an SRAM array, wherein the plurality of SRAM cells provide a physically unclonable function (PUF). A PUF evaluation engine includes a selection circuit for selecting one or more word lines coupled to the plurality of SRAM cells in response to a challenge, and a cross-coupled latch coupled to two bit lines corresponding to two different SRAM cells of the plurality of SRAM cells. The cross-coupled latch is configured to provide one of two 2-bit values depending on which of the two bit lines discharges faster upon the two different SRAM cells being selected by the selection circuit, wherein the 2-bit value is part of a digital code provided in response to the challenge.

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Austin, TX, United States of America

Nihaar N Mahatme