Commissariat a L'energie Atomique Et Aux Energies Alternatives

Centre National De La Recherche Scientifique

Applied Materials, Inc.

Commissariat &#xe0; L'energie Atomique Et Aux Energies Alternatives

Stmicroelectronics S.a.

Commissariat À L'énergie Atomique Et Aux Énergies Alternatives

Stmicroelectronics (crolles 2) Sas

Universite Joseph Fourier

Stmicroelectronics Gmbh

Universite Grenoble Alpes

Universit&#xe9; Grenoble Alpes

Nicolas Posseme

Stefan Landis

Laurent Grenouillet

Cyrille Le Royer

Lamia Nouri

Maud Vinet

Fabrice Nemouchi

Olivier Joubert

Sebastien Barnola

Yannick Le Tiec

Laurent J Vallier

Raluca Tiron

Xavier Chevalier

Srinivas D Nemani

Thorsten B Lill

Shay Reboh

Yves Morand

Perrine Batude

Louis Hutin

Laurent Brunet

Hubert Teyssedre

Nicolas J Loubet

Samer Banna

Lei Lian

Christophe Navarro

Emmanuel Augendre

Sébastien Kerdiles

Olivier Pollet

Christian Arvet

Thibaut David

Maxime Garcia-Barros

Valentin Bacquie

Loic Gaben

Sylvain Maitrejean

Sylvain Barraud

Maxime Darnon

Gene S Lee

Jean Berthier

Frederic-Xavier Gaillard

Maxime Argoud

Léa Di Cioccio

Sebastien Lagrasta

Marie-Anne Jaud

Sébastien Barnola

Frédéric-Xavier Gaillard

Zouhir Mehrez

Patricia Pimenta Barros

Jerome Mazurier

Michael May

François Lefloch

Guillaume Claveau

Pierre Brianceau

Gilles Cunge

Emilie Despiau-Pujo

Christophe Vallee

Frederic Le Roux

Aurélien Sarrazin

Vincent Ah-Leung

Yann Mazel

Marceline Bonvalot

Erwine Pargon

Frédéric Le Roux

Ahmad Chaker

Clemens Fitz

Elisa Vermande

Loïc Gaben

Stéphan Landis

Fr D Ric-Xavier Gaillard

Jérôme Mazurier

A semiconductor device made on a substrate including an active region and a non-active region at least partially surrounding the active region, a plurality of gate stacks, a part of each gate stack being on the active region, each gate stack being separated from adjacent gate stacks by a spacer by a distance e, the device being such that, for each gate stack, the part of the gate stack located on the active region has a height h, the part of the same gate stack located on the non-active region has a height h, and h/e=aand h/e=a<awhere ais an aspect ratio such that, upon growth of the spacer material forming the spacers, an airgap is in the spacer, and ais an aspect ratio such that, upon growth of the spacer material forming the spacers, no airgap is in the spacer.

Device comprising spacers including a localised airgap and associated manufacturing methods

A method is provided for etching a dielectric layer covering a top and a flank of a three-dimensional structure, the method including: a first etching of the dielectric layer, including: a first fluorine-based compound and oxygen, the first etching being performed to: form a first protective layer on the top and form a second protective layer on the dielectric layer, a second etching configured to remove the second protective layer while retaining a portion of the first protective layer, the first and the second etchings being repeated until removing the dielectric layer located on the flank of the structure, and before deposition of the dielectric layer, a formation of an intermediate protective layer between the top and the dielectric layer.

Method of engraving a three-dimensional dielectric layer

A method for forming spacers of a gate of a transistor is provided, including: providing an active layer surmounted by a gate; forming a dielectric layer covering the gate and the active layer, the dielectric layer having lateral portions, and basal portions covering the active layer; anisotropically modifying the basal portions by implantation of hydrogen-based ions in a direction parallel to the lateral sides of the gate, forming modified basal portions; annealing desorbing the hydrogen from the active layer and transforming the modified basal portions into second modified basal portions; and removing the modified basal portions by selective etching of the modified dielectric material with respect to the non-modified dielectric material and with respect to the semiconductive material, so as to form the spacers on the lateral sides of the gate.

Method of forming the spacers of a transistor gate

A method for manufacturing a mould for nanoprinting and the associated mould, includes providing a substrate having a layer, and at least one ion implantation configured so as to obtain in the layer, at least one first non-implanted portion or portion having a first implantation, at least one second portion having a second implantation, and a third non-implanted portion distinct from the first portion. After implantation, the method includes etching the layer configured so as to have a different etching speed between at least the second portion and the third portion, so as to etch through the openings of an etching mask, a plurality of patterns of different heights being included in the layer.

Method for manufacturing a mould for nanoprinting and associated mould

A method for increasing the surface roughness of a layer based on a metal having a catalytic power, includes fixing fluorine or chlorine on the surface of the metal based layer, by exposing the metal based layer to a plasma formed from a reactive gas containing fluorine or chlorine; exposing the surface of the metal based layer to a humid environment to produce an acid, by reaction of hydrogen from the humid environment with the fluorine or the chlorine fixed on the surface of the metal based layer, the acid reacting with the metal to form residues, the whole of the residues forming a pattern on the surface of the metal based layer, and etching the metal based layer through the residues, so as to transfer the pattern into the metal based layer.

Method for increasing the surface roughness of a metal layer

The invention relates to a method for making an individualization zone of a microchip comprising a first (A) and a second (A) level of electrical tracks (), and a conductor layer (A) comprising via holes (), the method comprising the following steps:

Method of making an individualization zone of an integrated circuit

A method for increasing the surface roughness of a metal layer, includes depositing on the metal layer a sacrificial layer made of a dielectric material including nitrogen; exposing a surface of the sacrificial layer to an etching plasma so as to create asperities; and etching the metal layer through the sacrificial layer, so as to transfer the asperities of the sacrificial layer into a part at least of the metal layer.

A method for making an individualization zone of a microchip comprising a first level and a second level of electrical tracks, and a level of interconnections comprising vias. The method includes: providing the first level and a dielectric layer, making a hard metal mask on the dielectric layer, etching the dielectric layer through the mask openings by etching based on fluorinated chemistry, preferably oxidizing the hard metal mask by hydrolysis so as to form randomly distributed residues at certain openings, and filling the openings so as to form at least the vias of the level of interconnections, the vias comprising functional vias at the openings without residues and inactive vias at the openings with residues.

A method is provided for forming spacers of a gate of a transistor, including: providing an active layer surmounted by a gate; forming a dielectric layer covering the gate and the active layer, the dielectric layer having lateral portions and basal portions; anisotropically modifying the basal portions by implantation of light ions, forming modified basal portions; and removing the modified basal portions by selective etching, so as to form the spacers on the lateral flanks of the gate from the unmodified lateral portions, in which, before the removing step, the anisotropic modification of the basal portions includes n successive implantation phases having implantation energies Γi (i=1 . . . n) which are distinct from each other, the n phases being configured to implant the light ions at different nominal implantation depths.

Method of forming the spacers on lateral flanks of a transistor gate using successive implantation phases

A method for producing a quantum device comprising providing a substrate having a front face and carrying at least one transistor pattern on the front face thereof, said transistor pattern comprising, in a stack a gate dielectric on the front face of the substrate, and a gate on the gate dielectric, said gate having a top and sidewalls. The method further includes forming a protective layer at the front face of the substrate, said protective layer being configured to prevent diffusion of at least one metal species in the substrate, forming a metal layer that has, as a main component, at least one metal species, at least on the sidewalls of the gate, said at least one metal species comprising at least one superconducting element, and forming a superconducting region in the gate by lateral diffusion of the at least one superconducting element from the sidewalls of said gate.

Method of making a quantum device

A method is provided for producing a plurality of transistors on a substrate comprising at least two adjacent active areas separated by at least one electrically-isolating area, each transistor of the plurality of transistors including a gate having a silicided portion, and first and second spacers on either side of the gate, the first spacers being located on sides of the gate and the second spacers being located on sides of the first spacers. The method includes forming the gates of the transistors, forming the first spacers, forming the second spacers, siliciding the gates so as to form the silicided portions of the gates, and removing the second spacers. The removal of the second spacers takes place during the silicidation of the gates and before the silicided portions are fully formed.

Method of manufacturing microelectronic components

A method for etching at least one layer of a gallium nitride (GaN)-based material is provided, the method including: providing the GaN-based layer having a front face; and at least one cycle including the following successive steps: modifying, by implanting hydrogen (H)- and/or helium (He)-based ions, at least some of a thickness of the GaN-based layer to form in the layer at least one modified portion extending from the front face, the implanting being carried out from a plasma, the modifying by implanting being carried out such that the modified portion extends from the front face and over a depth greater than 3 nm; oxidizing at least some of the modified portion by exposing the layer to an oxygen-based plasma, to define in the layer, at least one oxidized portion and at least one non-oxidized portion; and etching the oxidized portion selectively at the non-oxidized portion.

Method of etching a layer based on a III-V material

A method is provided for forming at least one trench to be filled with an isolating material to form an isolating trench, in a substrate based on a semiconductor material, the method including at least the following successive steps: providing a stack including at least the substrate, a first hard mask layer, and a second hard mask layer; making at least a first opening and a second opening, by carrying out isotropic etchings; performing a third, anisotropic, etching of the substrate in line with the second opening, so as to obtain the at least one trench; performing a fourth, isotropic, etching of the first layer so as to enlarge the first opening and obtain a first enlarged opening; and performing a fifth, anisotropic, etching so as to simultaneously enlarge the second opening and increase a depth of the at least one trench.

Method for forming trenches

Method for producing a semiconductor device, including:

Method for producing at least one device in compressive strained semiconductor

A method for forming reliefs on a face of a substrate is provided, successively including forming a protective screen for protecting at least a first zone of the face; an implanting to introduce at least one species comprising carbon into the substrate from the face of the substrate, the forming of the protective screen and the implanting being configured to form, in the substrate, at least one carbon modified layer having a concentration of implanted carbon greater than or equal to an etching threshold only from a second zone of the face of the substrate not protected by the protective screen; removing the protective screen; and etching the substrate from the first zone selectively with respect to the second zone.

Formation of reliefs on the surface of a substrate

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Sassenage, France

Nicolas Posseme