Soitec

S.o.i.tec Silicon on Insulator Technologies

S.o.i. Tec Silicon on Insulator Technologies, S.a.

International Business Machines Corporation

Commissariat a L'energie Atomique

Asm International N.v.

Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Nicolas Daval

Walter Schwarzenbach

Cécile Aulnette

Takeshi Akatsu

Nguyet-Phuong Nguyen

Guillaume Chabanne

Bich-Yen Nguyen

Ludovic Ecarnot

Konstantin Bourdelle

Bruno Ghyselen

Olivier Rayssac

Nadia Ben Mohamed

Ian Cayrefourcq

Cecile Aulnette

Stephen W Bedell

Keith E Fogel

Christophe Maleville

Sébastien Kerdiles

Christophe Figuet

Steven R A Van Aerde

Cornelius A Van Der Jeugd

Bénédite Osternaud

Carole David

Francois Boedt

Marinus J De Blank

Damien Massy

Oliver Rayssac

Zohra Chahra

Thierry Billon

Guillaume Besnard

Isabelle Guerin

Christophe Girard

François Templier

Romain Larderet

Marinus J M De Blank

François Boedt

Cécille Aulnette

A method for fabricating a strained semiconductor-on-insulator substrate comprises bonding a donor substrate to a receiving substrate with a dielectric layer at the interface. The donor substrate comprises a monocrystalline carrier substrate, an intermediate etch-stop layer, and a monocrystalline semiconductor layer. The monocrystalline semiconductor layer is transferred from the donor substrate to the receiving substrate. Trench isolations are formed to cut a portion from a layer stack including the transferred monocrystalline semiconductor layer, the dielectric layer, and the strained semiconductor material layer. The cutting operation results in relaxation of strain in the strained semiconductor material, and in application of strain to the transferred monocrystalline semiconductor layer. After transferring the monocrystalline semiconductor layer and before the cutting operation, a portion of the carrier substrate is selectively etched with respect to the intermediate layer, and the intermediate layer is selectively etched with respect to the monocrystalline semiconductor layer.

Method for fabricating a strained semiconductor-on-insulator substrate

A method of manufacturing a substrate for a front-facing image sensor, comprises:—providing a donor substrate comprising a semiconductor layer to be transferred,—providing a semiconductor carrier substrate,—bonding the donor substrate to the carrier substrate, an electrically insulating layer being at the bonding interface,—transferring the semiconductor layer to the carrier substrate,—implanting gaseous ions in the carrier substrate via the transferred semiconductor layer and the electrically insulating layer, and—after the implantation, epitaxially growing an additional semiconductor layer on the transferred semiconductor layer.

Method for manufacturing a substrate for a front-facing image sensor

A method for manufacturing a CFET device comprises forming a substrate of the double semi-conductor on insulator type, successively comprising, from the base to the surface thereof: a carrier substrate, a first electrically insulating layer, a first single-crystal semiconductor layer, a second electrically insulating layer and a second single-crystal semiconductor layer. Slices are formed into the substrate to the first electrically insulating layer so as to form at least one fin (F). A channel of a first transistor is formed in the first semiconductor layer and a channel of a second transistor is formed opposite the first transistor in the second semiconductor layer. Formation of the substrate of the double semi-conductor on insulator type comprises: a first and a second step of transferring a layer and thermal processing at a temperature that is sufficiently high to smooth the first single-crystal semiconductor layer to a roughness lower than 0.1 nm RMS.

Method for manufacturing a CFET device

A method for fabricating a strained semiconductor-on-insulator substrate includes bonding a donor substrate to a receiving substrate, with a dielectric layer at the interface, and transferring a monocrystalline semiconductor layer from the donor substrate to the receiving substrate. A portion is cut from a stack formed from the transferred monocrystalline semiconductor layer from the dielectric layer and from the strained semiconductor material layer. The cutting results in the relaxation of the strain in the strained semiconductor material, and in the application of at least a part of the strain to the transferred monocrystalline semiconductor layer. The method also involves the formation, on the strained semiconductor material layer of the receiving substrate, of a dielectric bonding layer or of a bonding layer consisting of the same relaxed, or at least partially relaxed, monocrystalline material as the monocrystalline semiconductor layer of the donor substrate.

A method for transferring a layer from a single-crystal substrate, called a donor substrate, onto a receiver substrate, includes supplying the single-crystal donor substrate, the substrate having a notch oriented in a first direction of the crystal and a weakness region bounding the layer to be transferred, bonding of the single-crystal donor substrate onto the receiver substrate, the main surface of the donor substrate opposite to the weakness region with respect to the layer to be transferred being at the bonding interface, and detachment of the donor substrate along the weakness region. In the method, the donor substrate has, on the main surface bonded to the receiver substrate, an array of atomic steps extending essentially in a second direction of the crystal different from the first direction.

Method for transferring a layer from a single-crystal substrate

The present disclosure relates to a method for the manufacture of a wafer by providing a doped layer on a semiconductor substrate; providing a first semiconductor layer on the doped layer; providing a buried oxide layer on the first semiconductor layer; and providing a second semiconductor layer on the buried oxide layer to form a wafer having a buried oxide layer and a doped layer beneath the buried oxide layer. The disclosure also relates to the wafer that is produced by the new method.

Wafer with intrinsic semiconductor layer

The present invention concerns a method for forming a Semiconductor-On-Insulator structure that includes a semiconductor layer of III/V material by growing a relaxed germanium layer on a donor substrate; growing at least one layer of III/V material on the layer of germanium; forming a cleaving plane in the relaxed germanium layer; transferring a cleaved part of the donor substrate to a support substrate, with the cleaved part being a part of the donor substrate cleaved at the cleaving plane that includes the at least one layer of III/V material. The present invention also concerns a germanium on III/V-On-Insulator structure, an N Field-Effect Transistor (NFET), a method for manufacturing an NFET, a P Field-Effect Transistor (PFET), and a method for manufacturing a PFET.

Method for forming a Ge on III/V-on-insulator structure

The present disclosure provides a chemical etchant which is capable of removing Ge and Ge-rich SiGe alloys in a controlled manner. The chemical etchant of the present disclosure includes a mixture of a halogen-containing acid, hydrogen peroxide, and water. Water is present in the mixture in an amount of greater than 90% by volume of the entire mixture. The present disclosure also provides a method of making such a chemical etchant. The method includes mixing, in any order, a halogen-containing acid and hydrogen peroxide to provide a halogen-containing acid/hydrogen peroxide mixture, and adding water to the halogen-containing acid/hydrogen peroxide mixture. Also disclosed is a method of etching a Ge or Ge-rich SiGe alloy utilizing the chemical etchant of the present application.

Etchant for controlled etching of Ge and Ge-rich silicon germanium alloys

The present invention relates to a method of forming a SOI structure having a thin silicon layer by forming a first etch stop layer on a donor substrate, forming a second etch stop layer on the first etch stop layer, wherein the material of the second etch stop layer differs from the material of the first etch stop layer, forming a thin silicon layer on the second etch stop layer, preferably by epitaxy, and bonding the intermediate structure to a target substrate, followed by detaching the donor substrate by splitting initiated in the first etch stop layer at a weakened region and removing the remaining material of the etch stop layers to produce a final ETSOI structure. The invention also relates to the ETSOI structure produces by the described method.

Manufacture of thin silicon-on-insulator (SOI) structures

A method for reducing roughness of an exposed surface of an insulator layer on a substrate, by depositing an insulator layer on a substrate wherein the insulator layer includes an exposed rough surface opposite the substrate, and then smoothing the exposed rough surface of the insulator layer by exposure to a gas plasma in a chamber. The chamber contains therein a gas at a pressure of greater than 0.25 Pa but less than 30 Pa, and the gas plasma is created using a radiofrequency generator applying to the insulator layer a power density greater than 0.6 W/cmbut less than 10 W/cmfor at least 10 seconds to less than 200 seconds. Substrate bonding and layer transfer may be carried out subsequently to transfer the thin layer of substrate and the insulator layer to a second substrate.

Method of reducing roughness of a thick insulating layer

The invention relates to a of manufacturing a silicon dioxide layer of low roughness, that includes depositing a layer of silicon dioxide over a substrate by a low pressure chemical vapor deposition (LPCVD) process, the deposition process employing simultaneously a flow of tetraethylorthosilicate (TEOS) as the source material for the film deposition and a flow of a diluant gas that it not reactive with TEOS, so that the diluant gas/TEOS flow ratio is between 0.5 and 100; and annealing the silicon dioxide layer at a temperature between 600&#xb0; C. and 1200&#xb0; C., for a duration between 10 minutes and 6 hours.

Method of manufacturing a silicon dioxide layer

The invention concerns a method for oxidizing a surface region of a SiGe layer that includes an oxidizing thermal treatment of the SiGe layer for oxidizing the surface region. The method includes two phases&#x2014;a first phase of oxidizing thermal treatment, carried out directly on the SiGe layer, so as to obtain an oxidized region which is thick enough for forming a capping oxide which can protect the underlying SiGe from pitting during the subsequent second phase, but thin enough for keeping the thickness of the oxidized surface region under a threshold thickness range, corresponding to the generation of dislocations within the SiGe layer; and&#x2014;a second phase of high temperature annealing in an inert atmosphere which is carried out on the SiGe layer after the first phase. The SiGe layer is capped with the oxidized region created during the first phase, and the high temperature annealing allows the diffusion of Ge from a Ge-enriched region into the underlying part of the SiGe layer.

Thermal oxidation of a SiGe layer and applications thereof

A method for manufacturing a semiconductor heterostructure by first manufacturing a donor wafer having a first substrate with a first in-plane lattice parameter, a spatially graded buffer layer having a second in-plane lattice parameter, and a strained smoothing layer of a semiconductor material having a third in-plane lattice parameter which has a value between that of the first and second lattice parameters. A top layer is formed on the ungraded layer a top layer of a semiconductor material having a top surface, optionally with a superficial layer present on the top surface and having a thickness that is equal to or smaller than 10 nanometers. Next, a handle wafer of a second substrate having an insulator layer thereon is bonded with the donor wafer in such way that (a) the insulator layer of the handle wafer is bonded directly onto the top surface of the top layer of the donor wafer, or (b) the insulator layer of the handle wafer is bonded onto the superficial layer.

Method of manufacturing a semiconductor heterostructure

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Grenoble, France

Nicolas Daval