Other

Mentor Graphics Corporation

Nicolas Bailey Cobb

Emile Y Sahouria

James C Word

Laurence W Grodd

Patrick Joseph LaCour

Yuri Granik

Eugene Miloslavsky

Leigh C Anderson

George P Lippincott

Kyohei Sakajiri

Siqiong You

Dragos S Dudau

Franklin Mark Schellenberg

Konstantinos G Adam

Raghu Prasad Chalasani

Sergiy Komirenko

Emin Martinian

Huikan Liu

A method of performing a resolution enhancement technique such as OPC on an initial layout description involves fragmenting a polygon that represents a feature to be created into a number of edge fragments. One or more of the edge fragments is assigned an initial simulation site at which the image intensity is calculated. Upon calculation of the image intensity, the position and/or number of initial simulation sites is varied. New calculations are made of the image intensity with the revised placement or number of simulation sites in order to calculate an OPC correction for the edge fragment. In other embodiments, fragmentation of a polygon is adjusted based on the image intensities calculated at the simulation sites. In one embodiment, the image intensity gradient vector calculated at the initial simulation sites is used to adjust the simulation sites and/or fragmentation of the polygon.

Fragmentation point and simulation site adjustment for resolution enhancement techniques

A set of original model candidates are first divided into groups of original model candidates. Child model candidates are generated by performing crossover on each of the groups of original model candidates without mutation. From the original model candidates and the child model candidates, a set of new model candidates are derived, which includes: selecting a group of new model candidates from each group of the original model candidates and the corresponding child model candidates, selecting an additional new model candidate if adding the additional new model candidate increases overall diversity, and performing niche clearing to keep a number of the new model candidates in each of niches from exceeding a maximum number. The dividing, generating and deriving operations are then iterated. Model caching may be performed by restricting the crossover to the model term level or above.

Lithography model calibration via cache-based niching genetic algorithms

Aspects of the invention relate to techniques for compensating flare effects in a lithographic process for an array of identical circuits to be fabricated on a wafer. According to various implementations of the invention, a reference circuit is selected from the array of identical circuits and intolerable flare difference regions are determined based on flare difference layers and tolerable flare difference layers. The lithographic process result for the array of identical circuit may be derived from that for the reference circuit and the intolerable flare difference regions.

Tolerable flare difference determination

An integrated verification and manufacturability tool provides more efficient verification of integrated device designs than verification using several different verification components. The integrated verification and manufacturability includes a hierarchical database to store shared design data accessed by multiple verification components (e.g., layout versus schematic, design rule check, optical process correction, phase shift mask assignment and OPC verification and machine language conversion). The hierarchical database includes representations of one or more additional, or intermediate layer structures that are created and used by the verification components for operations performed on the design being verified. Use of a single hierarchical database having shared data for access and use by multiple verification components streamlines the verification process, which provides an improved verification tool.

Integrated OPC verification tool

After layout design data has been modified using an OPC process, a repair flow is initiated. This repair flow includes analyzing the modified data to identify any remaining or new potential print errors in the layout data. Regions then are formed around the identified potential print errors, and a subsequent OPC process is performed only on the data within these regions using a different set of process parameters from the process parameters employed by the initial OPC process. This repair flow is iteratively repeated, where a different set of process parameter values for the subsequent OPC process is used during each iteration.

Selective optical proximity layout design data correction

A method of calculating process conditions for performing optical and process correction (OPC) or other resolution enhancement techniques on a layout design. Process conditions are estimated on a layout database on a substantially uniform grid. Contour curves are created from the estimated process conditions. The contour curves are then compared against the features in the layout to determine edge placement errors. From the edge placement errors, OPC or other corrections for the features can be made.

Dense OPC

Layout correction is accomplished using a forward mapping technique. Forward mapping refers to mapping of fragments from a reticle layout to a target layout, while backward mapping refers to mapping of fragments from the target layout to the reticle layout. Forward mapping provides a technique for making an unambiguous mapping for each reticle fragment to a corresponding target layout fragment. The mapping does not necessarily provide a one-to-one correspondence between reticle fragments and target layout fragments. That is, multiple reticle layout fragments can map to a single target layout fragment. An edge placement error for the target layout fragments is used to make positioning corrections for the corresponding reticle fragment(s). Edge placement error can be determined, for example, with a simulation process that simulates a manufacturing process using the reticles.

Convergence technique for model-based optical and process correction

A method of preparing a file that stores layout of devices to be created with photolithography for optical and process correction (OPC). Polygons that define structures to be created are initially fragmented into edge segments and a simulation of how the edge segments will be printed under process conditions is performed. The results of the simulation are used to adjust/refragment the edge segments. In one embodiment, the curvature of light intensity at the edge segments is used to adjust the fragmentation of the polygons.

Method and apparatus for performing OPC using model curvature

A tool for optimizing the layout of a microdevice adds fragmentation points to polygons in a first hierarchical database layer in a manner suitable for application of a tool to apply a resolution enhancement technique (RET) such as optical and process correction (OPC). Portions of polygons in a database level that interact with polygons of a second level in the database are promoted to the second database level, and refragmented. The RET operates on the polygons of the first and second levels of the database to determine how polygons of each of the first and second levels should be adjusted, if necessary, such that the layout is optimized.

Selective promotion for resolution enhancement techniques

A method for performing a matrix-based verification technique such as optical process correction (OPC) that analyzes interactions between movement of a fragment on a mask and one or more edges to be created on a wafer. In one embodiment, each edge to be created is analyzed and one or more fragments of a mask are moved in accordance with a gradient matrix that defines how changes in position of a fragment affect one or more edges on the mask. Fragments are moved having a significant effect on an edge in question. Simulations are performed and fragments are moved in an iterative fashion until each edge has a objective within a prescribed tolerance. In another embodiment, each edge has two or more objectives to be optimized. A objective is selected in accordance with a cost function and fragments are moved in a mask layout until each edge has acceptable specification for each objective.

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Sunnyvale, CA, United States of America

Nicolas Bailey Cobb